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Electromagnetic ANSYS-MAXWELL Professional L&amp;T Technology Services is hiring Electromagnetic ANSYS-MAXWELL Professional for our Vadodara location.Experience-10-16 Years Description<ul><li>Hands on experience on High frequency and Low frequency electromagnetic simulation.</li><li>Electrostatic analysis for capacitance analysis, Creepage and Clearance of electrical products.</li><li>Electromagnetic analysis for Electric motors and actuators, inductor, coil, etc.</li><li>High Frequency simulation for EMI, EMC analysis</li><li>Battery Modelling and analysis for Electric vehicle system level simulation. Pre processing and Post Processing in COMSOL, ANSYS Maxwell, ALTAIR FLUX</li><li>Excellent communication skills to discuss the project with its stakeholder</li></ul> Required Skill: ELECTROMAGNETICS, ELECTROSTATICS, COMSOL, ANSYS-MAXWELL, HFSS, ALTAIR-FLUX, FEKO

L&T Technology Services Ltd

Junior Electrical Engineer

Durability Engineer (Abaqus) We're hiring below position: Skills: Durability Engineer (Abaqus)Experience: 4 to 6 yearsLocation: Chennai If interested, share your CV.

Capgemini Engineering

Fabrication Engineer

Subcontractor<h4>Area(s) of responsibility</h4>JD - Windchill DeveloperResponsibilities:<ul><li>Configure, Customize &amp; Build solutions aligned with business process and requirements.</li><li>Develop applications using Windchill’s REST API, </li><li>Deploy and debug code through build process and with accordance to best practices throughout the development lifecycle.</li><li>Work closely with onshore/offshore Business/Solution Architects and support them in developing prototypes and implementing full solutions.</li><li>Understand the technical requirements and develop detailed design documents.</li><li>Coordinate support activities and identify solutions for complex issues.</li><li>Develop code with minimum supervision, that meets quality standards and best practices.</li><li>Provide unit and functional test-cases for the implemented solutions.</li></ul> Knowledge/Skills, Education, and Experience<ul><li>5-7 years of experience in configuring and customizing Windchill PLM and related modules</li><li>Ability to install, configure and upgrade Windchill and prior experience with integrations is a plus.</li></ul><h4>Experience Level</h4>Senior Level

Birlasoft Limited

Developer

EOIR EngineerResponsible for assembly and testing of Electro-Optical Infrared (EO/IR) system.


Responsible to develop the complete EOIR system


Responsible to carry out sensor bore-sighting.


Responsible to carry out Fine tuning of sensors and lens.


Responsible to conduct environmental tests for EOIR system.     


Responsible for field testing of system.


Hands-on experience on Laser test equipment’s like power meter, M2 measurement unit, beam profiler, thermal imager.



Bachelor's degree in Electronics/Mechanical/Opto electronics EngineeringExperience:<ul><li>Work experience as an EOIR System for min 5 years</li><li>Knowledge of Electro-Optical Infrared (EO/IR) Assembly.</li><li>Knowledge of sensor bore-sighting</li><li>Knowledge of Fine tuning of sensors and lens.</li><li>Hands-on experience on Laser test equipment’s like power meter, M2 measurement unit, beam profiler, thermal image</li></ul><h4>Experience Level</h4>Mid Level

Adani Enterprises Ltd

Engineer

Engineering Manager(Firmware), Systems TeamWe’re in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry.This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.SHOULD YOU ACCEPT THIS CHALLENGE...The DFM Firmware Team plays a crucial role in designing and developing the Direct Flash Module (DFM) – a key module of Pure's Flasharray and Flashblade enterprise storage solutions. The DFM is an internally designed enterprise storage device using the NAND flash technology. Compared with the off-the-shelf SSD, the DFM has the competitive advantage of  simplicity, high performance, low cost and scalability.As a leader of the DFM firmware team, you'll have rare opportunities to work across various domains, including the entire data path, NAND media management, and low-level hardware interfaces. Our firmware design enables us to quickly integrate the latest NAND technologies from various vendors. We were pioneers in adopting QLC for enterprise storage solutions, releasing the first QLC DFM in 2019. Our proprietary media management policies and algorithms position Pure as a leader in enabling QLC NAND in the enterprise storage industry.You'll work closely with the Purity software, hardware, NAND, and drive qualification teams. This offers a unique opportunity to learn the latest technologies, including the newest generations of NAND, NVMe/PCIe, as well as SSD controllers. Firmware development opens doors to experiences in embedded software design, hardware and system integration. You'll develop a comprehensive understanding and gain insights into the entire product development and release process.What You Will Be Doing…<ul><li>Project Management: Collaborate with program teams to manage firmware project schedules, deliverables, dependencies, risks, and resources effectively.</li><li>Agile Leadership: Lead the team sprints, set sprint goals, manage the backlog, and prioritize tasks to ensure efficient and iterative development.</li><li>Process Improvement: Continuously improve the firmware team productivity and engineering development processes to enhance product quality and development speed.</li><li>Team Development: Manage team performance, conduct 1-on-1 meetings, provide timely feedback, and contribute to the professional growth and development of team members.</li></ul>What You Bring To The Team...<ul><li>12+ years experience in SSD/Storage/Embedded domain along with excellent FW &amp; HW debug skills</li><li>3+ years of experience in technical leadership or management roles focused on embedded systems.</li><li>B.E. or M.E in Electrical Eng, Electronics &amp; Communication Eng, Computer Eng</li><li>Proficiency in C/C++ and Python programming languages.</li><li>Understanding of hardware-software interface; knowledge of SSD controllers or NAND is a plus.</li><li>Expertise in Agile development and continuous integration practices, with a track record of managing projects throughout the entire product development cycle.</li><li>Strong communication skills, both verbal and written, enabling effective collaboration with cross-functional teams and stakeholders.</li><li>Demonstrated analytical and problem-solving abilities, with a keen eye for detail and quality.</li><li>Proven ability to deliver projects to market on schedule and gather customer feedback for continuous improvement.</li></ul> <ul><li>We are primarily an in-office environment and therefore, you will be expected to work from the Banglaore office in compliance with Pure’s policies, unless you are on PTO, or work travel, or other approved leave.</li></ul>WHAT YOU CAN EXPECT FROM US:<ul><li>Pure Innovation: We celebrate those who think critically, like a challenge and aspire to be trailblazers.</li><li>Pure Growth: We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area™, Fortune's Best Workplaces for Millennials™ and certified as a Great Place to Work®!</li><li>Pure Team: We build each other up and set aside ego for the greater good.</li></ul>And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out <a href="http://purebenefits.com">purebenefits.com</a> for more information.ACCOMMODATIONS AND ACCESSIBILITY:Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at <a href="mailto:TA-Ops@purestorage.com">TA-Ops@purestorage.com</a> if you’re invited to an interview.OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM:We’re forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn’t just accepted but embraced. That’s why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership. Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.<h4>Experience Level</h4>Senior Level

Pure Storage India Pvt Ltd

Engineering Manager

DFT Engineer <ul><li>Skill: DFT, ATPG, Scan Insertion</li><li>Experience: 4+ years</li><li>Notice Period: Immediate-15 Days</li></ul> Share your updated resume now.

ACL Digital

Testing Engineer

Physical Design Engineer - Foundry Team As one of the largest R&amp;D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.&nbsp; ﻿Roles and Responsibilities<ul><li>Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA , timing and physical signoffs</li><li>Hands on experience doing physical design and timing closure of complex blocks and full-chip designs.</li><li>Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus.</li><li>Should have strong understanding of timing, power and area trade-offs and optimization of PPA.</li><li>Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities.</li><li>Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows.</li><li>Experience with large SOC designs (&gt;20M gates) with frequencies in excess of 1GHZ .</li><li>Expertise in block level and full-chip SDC clean up, Synthesis optimization , Low Power checking and logic equivalence checking.</li><li>Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling).</li><li>Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.</li><li>Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence.</li><li>Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.</li><li>Should have gone through recent successful SOC tape-outs.</li></ul> Experience – 5+ Years of experience Qualifications<ul><li>B.Tech/B.E/M.Tech/M.E</li></ul>

Samsung India Electronics Pvt Ltd 

Design Engineer

Chief EngineerJLL empowers you to shape a brighter way.  Our people at JLL and JLL Technologies are shaping the future of real estate for a better world by combining world class services, advisory and technology for our clients. We are committed to hiring the best, most talented people  and empowering them to  thrive, grow meaningful careers and to find a place where they belong.  Whether you’ve got deep experience in commercial real estate, skilled trades or technology, or you’re looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward.   Roles &amp; Responsibility: -Roles &amp; Responsibility: -Critical Equipment Management:<ul><li>Hi Side Equipment Management</li></ul><ul><li>Lead the engineering team in evaluating, selecting, and acquiring cutting-edge semiconductor equipment.</li><li>Collaborate with vendors to assess equipment performance and plan upgrades for advanced technology adoption.</li><li>Implement strategies to enhance equipment reliability and reduce mean time to repair (MTTR).</li><li>Facilitate collaboration with vendors to ensure seamless integration of new equipment into the lab environment.</li></ul><ul><li>Scrubber Management</li></ul><ul><li>Develop and implement protocols for efficient operation and maintenance of scrubbers.</li><li>Conduct regular assessments to ensure scrubbers meet air quality standards.</li><li>Implement improvements to enhance the overall effectiveness of scrubber systems.</li></ul><ul><li>Toxic Gases Management</li></ul><ul><li>Develop and enforce strict protocols for the safe handling, storage, and disposal of toxic gases.</li><li>Conduct regular safety drills and training sessions for team members on handling toxic gases.</li><li>Collaborate with vendors to enhance gas detection systems and implement advanced safety features.</li></ul><ul><li>ETP Management</li></ul><ul><li>Optimize ETP performance to meet wastewater treatment standards and regulatory requirements.</li><li>Collaborate with environmental engineers to implement advanced technologies for ETP efficiency.</li><li>Implement preventive maintenance programs to minimize downtime and ensure continuous ETP operation.</li></ul><ul><li>Gas Panel Management</li></ul><ul><li>Collaborate in the design and optimization of gas panel systems for semiconductor processes.</li><li>Implement safety measures and protocols related to gas panel operation.</li><li>Train team members on gas panel operation and emergency procedures.</li></ul>Project &amp; Operation Management – <ul><li>Project Management</li></ul><ul><li>Lead complex projects such as lab expansions, infrastructure upgrades, and facility improvements.</li><li>Collaborate with architects, Designers, contractors, and other stakeholders for effective project execution.</li><li>Implement project management best practices, ensuring timely completion within budget constraints.</li></ul><ul><li>EHS Management</li></ul><ul><li>Oversee EHS initiatives within the engineering department, ensuring compliance and best practices.</li><li>Collaborate with EHS teams to integrate safety measures into engineering processes.</li><li>Implement measures to enhance the overall well-being and safety of engineering team members.</li></ul><ul><li>Vendor Management</li></ul><ul><li>Collaborate with vendors for equipment procurement, maintenance, and services, ensuring cost-effectiveness and quality.</li></ul><ul><li>Budget Management</li></ul><ul><li>Collaborate in budget planning, ensuring financial resources are allocated effectively for engineering projects.</li></ul><ul><li>Team Leadership</li></ul><ul><li>Provide strong leadership to a multidisciplinary team of engineers and technicians, fostering a culture of innovation and excellence.</li><li>Establish and communicate team goals aligned with the lab's strategic objectives.</li><li>Conduct performance evaluations and implement career development plans for team members.</li><li>Implement continuous improvement initiatives and recognize team achievements.</li></ul>Compliance &amp; Governance -<ul><li>Risk Management</li></ul><ul><li>Assess and manage risks associated with engineering projects, ensuring proactive risk mitigation measures.</li></ul><ul><li>Compliance &amp; Audits</li></ul><ul><li>Lead the development and implementation of robust safety protocols and compliance standards.</li><li>Stay abreast of industry standards and regulatory requirements, implementing necessary changes in protocols and procedures.</li><li>Interface with regulatory agencies to ensure the lab's compliance with environmental and safety regulations.</li></ul><ul><li>ESG Responsibilities</li></ul><ul><li>Integrate ESG considerations into the decision-making process for facility projects and operations.</li><li>Develop strategies to reduce the lab's environmental impact and promote social responsibility.</li><li>Implement measures to enhance diversity and inclusion within the engineering team and the lab.</li><li>Collaborate with cross-functional teams to incorporate ESG considerations into lab design and operations.</li></ul><ul><li>Regulatory Affairs</li></ul><ul><li>Monitor and ensure compliance with relevant regulations and standards governing engineering projects and lab operations.</li></ul><ul><li>Data Security and Intellectual Property Protection</li></ul><ul><li>Collaborate with IT and security teams to ensure data security and intellectual property protection measures are in place.</li></ul>Energy, Innovation &amp; Quality – <ul><li>Energy Efficiency and Sustainability</li></ul><ul><li>Integrate energy-efficient solutions into engineering projects, promoting sustainability in lab operations.</li><li>Implement strategies to improve energy efficiency and enhance sustainability.</li><li>Lead the adoption of innovative technologies in engineering projects.</li></ul><ul><li>Emergency Response and Continuity Planning</li></ul><ul><li>Implement and test emergency response plans for engineering projects, minimizing disruptions.</li></ul><ul><li>Collaboration with Research and Development Teams</li></ul><ul><li>Collaborate with R&amp;D teams to align engineering projects with research goals and facilitate seamless integration.</li></ul><ul><li>Space Utilization and Optimization</li></ul><ul><li>Collaborate in lab design and layout planning to optimize space utilization for engineering projects and team efficiency.</li></ul><ul><li>Innovation and Technology Adoption</li></ul><ul><li>Advocate for the adoption of innovative technologies in engineering projects, keeping the lab at the forefront of industry advancements.</li></ul><ul><li>Quality Management</li></ul><ul><li>Incorporate quality management practices into engineering processes to deliver high-quality results and meet industry standards.</li></ul>Standards, Community, and Training –<ul><li>International Standards (ISO)</li></ul><ul><li>Ensure compliance with ISO standards applicable to engineering practices, contributing to the lab's overall certification efforts.</li></ul><ul><li>Community Engagement</li></ul><ul><li>Represent the lab in community engagement initiatives and promote a positive image through outreach and collaboration.</li></ul><ul><li>Training and Development</li></ul><ul><li>Provide ongoing training for engineering team members to enhance skills and keep them informed about technological advancements.</li></ul>Execution of Safety Protocols -<ul><li>Strict adherence to cleanroom protocols to minimize contamination.</li><li>Comprehensive training on the proper handling, storage, and disposal of chemicals.</li><li>Regular equipment inspections and maintenance to ensure safe operation.</li><li>Implementation of lockout/tagout procedures to prevent accidental equipment activation during maintenance.</li><li>Mandating the use of appropriate PPE, including safety glasses, face shields, gloves, and specialized protective clothing.</li><li>Development and regular testing of emergency response plans for various scenarios.</li><li>Installation of gas detection systems to monitor and alert personnel to the presence of toxic gases.</li><li>Regular calibration and maintenance of gas monitoring equipment.</li><li>Comprehensive training programs on safety procedures, chemical hazards, and emergency response.</li><li>Ongoing education to keep employees informed about the latest safety protocols and industry best practices.</li><li>Access to and understanding of Material Safety Data Sheets (MSDS) for all chemicals used in the semiconductor manufacturing process.</li><li>Collaboration with regulatory agencies to ensure compliance with environmental and safety regulations.</li><li>Implementation of advanced air filtration and ventilation systems to maintain a clean and safe working environment.</li><li>Monitoring and regular maintenance of air quality control systems.</li><li>Adherence to specific safety guidelines for handling semiconductor manufacturing tools.</li><li>Proper training on tool operation and maintenance.</li><li>Implementation of continuous improvement programs to identify and address safety concerns.</li><li>Regular safety audits and reviews to enhance overall safety performance.</li></ul>Qualifications:<ul><li>Minimum requirement: B-Tech/BE (Mechanical/Electrical/Civil &amp; Environmental engineering)</li><li>Preferred: - Master’s or Ph.D. in a related engineering field.</li><li>Additional Qualification –</li></ul><ul><li>Substantial experience in health care Manufacturing or R&amp;D labs in Pharmaceutical or semiconductor Industry.</li><li>Certifications in facility management, project management, environmental management may be advantageous.</li></ul>Location: On-site –Bengaluru, KAScheduled Weekly Hours:48If this job description resonates with you, we encourage you to apply even if you don’t meet all of the requirements.  We’re interested in getting to know you and what you bring to the table!JLL Privacy NoticeJones Lang LaSalle (JLL), together with its subsidiaries and affiliates, is a leading global provider of real estate and investment management services. We take our responsibility to protect the personal information provided to us seriously. Generally the personal information we collect from you are for the purposes of processing in connection with JLL’s recruitment process. We endeavour to keep your personal information secure with appropriate level of security and keep for as long as we need it for legitimate business or legal reasons. We will then delete it safely and securely.For more information about how JLL processes your personal data, please view our <a href='\"https://www.us.jll.com/en/careers/candidate-privacy-statement\"' target='\"_blank\"'>Candidate Privacy Statement</a>.For additional details please see our career site pages for each country.For candidates in the United States, please see a full copy of our Equal Employment Opportunity and Affirmative Action policy <a href='\"https://www.us.jll.com/en/careers/disclaimers\"' target='\"_blank\"'>here</a>.Jones Lang LaSalle (“JLL”) is an Equal Opportunity Employer and is committed to working with and providing reasonable accommodations to individuals with disabilities.  If you need a reasonable accommodation because of a disability for any part of the employment process – including the online application and/or overall selection process –  you may contact us at <a href='\"http://link.jll.com/Accommodation_Requests\"' target='\"_blank\"'>Accommodation Requests</a>. This email is only to request an accommodation. Please direct any other general recruiting inquiries to our <a href='\"https://www.us.jll.com/en/contact-us\"' target='\"_blank\"'>Contact Us</a> page &gt; I want to work for JLL.

Jones Lang Lasalle Property Consultants India Pvt Ltd

Chief Engineer

Proposal Engineer (Hydrocarbon / Fiscal metering Segment)Job Summary:Engaging with the Emerson Sales team and crafting professional proposals that address customer needs while highlighting the advantages of partnering with Emerson. In this Role, Your Responsibilities Will Be:<ul><li>Engaging with Sales Team - Collaborate closely with the Sales team. Understand their insights, customer interactions, and market dynamics. Effective communication is key.</li><li>Leading Diamond Model Collaborators - As a leader, guide the team throughout the proposal execution process. Ensure alignment with strategic goals.</li><li>Developing Execution Strategies - Supply to the development of execution strategies. These strategies should align with the overall business objectives.</li><li>Customer Enquiries and Specifications - Receive and interpret customer enquiries. Understand their specifications and challenges. Tailor proposals accordingly.</li><li>Collaboration with Operations and Suppliers - Work closely with Operations organization, Engineering centers, and Third-party suppliers. Review proposal strategies together.</li><li>PMO Proposal Workflow - Enforce guidelines, and procedures. Consistency streamlines execution.</li><li>Vendor RFQ and Quote Evaluation - Independently handle vendor Requests for Quotation (RFQ) and evaluate quotes. Make informed decisions.</li><li>Local Weights and Measures (WTs) - Be aware of local Weights and Measures requirements. Compliance is essential.</li><li>Contribute to Proposals initiatives to improve process efficiency, help avoiding repetitive mistakes and improve turn around.</li><li>Support new members development and bringing them onboard.</li><li>Engage in cross function initiatives, connect with cross function leaders and help resolving issues boosting collaboration between different functions.</li></ul>Who You Are:You show a tremendous amount of initiative in tough situations; is exceptional at spotting and seizing opportunities. You actively seek guidance from pertinent sources to make timely and well-informed decisions. You articulate messages in a way that is broadly understandableFor This Role, You Will Need:<ul><li>Good knowledge in application of various types of meters, analyzers and key product types and applications for gas &amp; liquids measurement. Proven understanding of applicable industry codes and standards such as ASME, ANSI, API, API MPMS, ISO &amp; other industry standards related to solutions.</li><li>Proficiency to be able to size flow meter and valves.</li><li>Good communication and interpersonal skills.</li><li>Good analytical skills and committed.</li><li>Flexibility to learn new things and understand different cultures.                         </li></ul>Preferred Qualifications that Set You Apart:<ul><li>BE/B.Tech in Instrumentation, Mechanical Engineering.</li><li>02 to 10 years of experience in segment specific applications, preferred experience in leading concurrent mid complexity proposals.</li><li>Participate in Buddy Program and coach newly joined team members. </li><li>Good knowledge about MS-Office applications.</li></ul> Our Culture &amp; Commitment to YouAt Emerson, we prioritize a workplace where every employee is valued, respected, and empowered to grow. We cultivate an environment that encourages innovation, collaboration, and diverse perspectives—because we know that great ideas come from great teams. Our commitment to ongoing career development and growing an inclusive culture ensures you have the support to thrive. Whether through mentorship, training, or leadership opportunities, we invest in your success so you can make a lasting impact. We believe diverse teams, working together are key to driving growth and delivering business results. We recognize the importance of employee wellbeing. We prioritize providing competitive benefits plans, a variety of medical insurance plans, Employee Assistance Program, employee resource groups, recognition, and much more. Our culture offers flexible time off plans, including paid parental leave (maternal and paternal), vacation and holiday leave. <h4>Experience Level</h4>Senior Level

Emerson Electric Company India Pvt Ltd

Technical Sales Engineer

Principal Engineer We are hiring Principal Engineer (Network Domain)<ul><li>Location: Bangalore (Work from Office)</li><li>Notice period: Immediate joiners up to 60 days</li><li>Experience : 10+years</li></ul> Share your updated cv to <a rel="noopener noreferrer" href="\&quot;mailto:neetika_yadav@onwardgroup.com\&quot;" target="_blank">neetika_yadav@onwardgroup.com</a>

Onward Technologies Limited

Silicon Micro-architecture and RTL Lead , Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.</li><li>10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).</li><li>Experience in micro-architecture and design IPs and Subsystems.</li><li>Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).</li></ul> <h4>Preferred qualifications:</h4><ul><li>Experience with scripting languages (e.g., Python or Perl).</li><li>Experience in SoC designs and integration flows.</li><li>Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies..</li><li>Knowledge of high performance and low power design techniques.</li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.<h4>Responsibilities</h4><ul><li>Drive development of Complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization.</li><li>Own micro-architecture and implementation of IPs and subsystems.</li><li>Work with Architecture, Firmware and Software teams to drive feature closure and develop micro-architecture specifications.</li><li>Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Identify and drive Power, Performance and Area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Senior Level

Google India Pvt Ltd

Embedded Systems Engineer

Silicon Networking RTL Design Senior Engineer, Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.</li><li>8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.</li><li>Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).</li><li>Experience in micro-architecture and design of IPs and subsystems in Networking domain such as packet processing, bandwidth management, congestion control, etc.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Experience with scripting languages (e.g., Python or Perl).</li><li>Experience in SoC designs and integration flows.</li><li>Knowledge of high performance and low power design techniques.</li><li>Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.</li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The ML, Systems, &amp; Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.<h4>Responsibilities</h4><ul><li>Own microarchitecture and implementation of complex IPs and subsystems in the Networking domain.</li><li>Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications. </li><li>Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Identify and lead power, performance, and area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Senior Level

Electronic Engineer

Linux Device Driver Developer Capgemini is hiring for Linux Device Driver Developer (LDD) can join in 30 Days, and possess the required skill set, apply to this job. Experience: 4- 10 years Key Requirements:1. 3-5 Yrs of experience in Embedded Linux Kernel/Drivers domain2. Embedded Software development and porting on Linux and ARM platforms3. Strong Programming skills on C &amp; Data Structures4. Expertise on OS (Memory Mgmt, Scheduling, IPC, Multi-threading/processing)5. Experience in Linux Kernel/Device Drivers6. Proficiency in debugging embedded systems, including using tools like JTAG7. Understanding of System architecture and debugging at a system level. Please send your resume with the following details:Subject Line: Job Application- LDD (Linux Device Drivers)Name:Total Exp:Rel exp:Current CTC:ECTC:Current location:Are you willing to relocate?Notice period/ LWD:

Capgemini

Linux Engineer

ASIC RTL Design Engineer Capgemini is hiring for below role: Position: ASIC RTL Design EngineerExperience: 5+yrsLocation: Bangalore .Note: Considering only ASIC experience candidates. Interested candidate share profile via email.

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