ASIC Design for Test (DFT) Engineer

ASIC DFT Engineer, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  
• 3 years of experience with SoC-level design for test (DFT) architecture, implementation, and validation.
• Experience with SoC DFT RTL implementation, RTL verification, ATPG/ MBIST/BSCAN/IDDQ pattern generation.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
  
• Experience with silicon process and technology nodes for high speed and low power consumption.
  

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will drive the SoC-level design for test (DFT ) architecture, implementation, and validation. Your role combines high-level architectural planning with automation, SoC DFT RTL implementation, RTL verification, automatic test pattern generation (ATPG)/memory built-in self-test (MBIST)/boundary scan (BSCAN)/current drain-to-drain quiescent (IDDQ) pattern generation, validation and ATE production support, directly impacting the reliability and scalability of Google’s custom hardware.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.In this role, you will drive the SoC-level design for test (DFT ) architecture, implementation, and validation. Your role combines high-level architectural planning with automation, SoC DFT RTL implementation, RTL verification, automatic test pattern generation (ATPG)/memory built-in self-test (MBIST)/boundary scan (BSCAN)/current drain-to-drain quiescent (IDDQ) pattern generation, validation and ATE production support, directly impacting the reliability and scalability of Google’s custom hardware.

Responsibilities

• Develop test patterns that optimally tests the logic/memory/analog macro under test.
• Work with internal cross-functional teams, external silicon partners, Product Engineering team, and intellectual property (IP) vendors to support structural validate and parametrically characterize the Silicon.
  
• Collaborate with cross-functional teams to debug failures (e.g., boards, software, manufacturing, design, thermal issues).
  

Experience Level

Mid Level