ASIC Engineer 3

ASIC DV Engineer

Experience: 5+ years

Responsibilities:

• You will be exposed to the latest verification methodologies like UVM and enable complex feature verification suites.
• Architect and Develop block level verification environments for sub-system and fullchip using System Verilog and UVM methodology. (30%)
• Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems. Use various front-end simulator tools (VCS/NC) to perform this activity. (25%)
• Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation. (30%)
• Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development. (10%)
• Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology (5%)

Required Skills:

• ASIC Verification using SystemVerilog
• Experience in constrained-random verification is a strong plus
• Experience with verification methodology like OVM/VMM/UVM
• Perl/Tcl scripting is strongly preferred
• Experience verifying networking protocols such as Ethernet is desirable
• Strong problem solving and ASIC debugging skills
• MSEE or BSEE is required with at least 5 years of ASIC Verification Experience.

ASIC Design Engineer

Experience: 5+ years

• As part of our fast-paced chip design group, you will become an expert in building high-speed ASICs, from specifications to final netlist. You can pick and choose where you want to work on – design/ verification or timing closure/PD. As you are getting started in your career, we will let you explore your passions here.  
• Open communications, empowerment, innovation, teamwork and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements and rewards.  

Responsibilities: 

• You will start with a functional specification of a module and come up with a detailed micro-architecture specification – do not worry, you will have guidance from our senior engineers on how to go about this if you have not done this before. 
• RTL coding – we prefer you know System Verilog and have done several school/intern projects (coding to synthesis) using this language. 
• Write functional coverage/SVA (we will teach you how to do this if you haven’t done this before)  
• Timing closure – work with PD to identify timing paths and fix timing in RTL to meet the frequency target.  
• Debug issues in your block found by verification team.  
• Use state-of-the-art EDA tools for various design checks.  

Recommended skills 

• Bachelor’s degree in Electrical Engineering required, Master’s strongly desired.  
• Strong analytical/ problem solving skills. 
• Should have taken courses for credit in digital logic design.  
• Strong coding skills in Verilog/System Verilog through courses and intern projects 
• Knowledge of Computer Architecture/networking protocols/machine learning through graduate level courses is a plus. 
• Excellent written and verbal communications skills is good to have. 
• Knowledge of Perl/Python is a plus