ASIC RTL Design Engineer

Minimum qualifications:

• Bachelor’s degree in Electrical/Computer Engineering.
• Experience with RTL design using Verilog/System Verilog and microarchitecture.
• Experience with a scripting language like Python or Perl.
• Experience with ARM-based SoCs, interconnects and ASIC methodology.

Preferred qualifications:

• Master’s degree in Electrical/Computer Engineering.
• 3 years of experience with IP design for clocking, interconnects, peripherals.
• Experience with methodologies for low power estimation, timing closure, synthesis.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).

Responsibilities

• Perform RTL development (SystemVerilog), debug functional/performance simulations.
• Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
• Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.
• Communicate and work with multi-disciplined and multi-site teams.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.