ASIC RTL Design Engineer, Silicon

Minimum qualifications:

• Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience.
• 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture.
• Experience in ARM-based SoCs, interconnects and ASIC methodology.

Preferred qualifications:

• Master’s degree in Electrical/Computer Engineering.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).
• Experience with methodologies for low power estimation, timing closure, synthesis.

Responsibilities

• Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc.
• Perform RTL development (SystemVerilog), debug functional/performance simulations.
• Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.
• Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up.
• Communicate and work with multi-disciplined and multi-site teams.

About the job

As part of our platform IP team, you will be a part of a team that designs foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver quality RTL. You will solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance and power.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.