Design Engineer - Semiconductor IP Integration and Quality Assurance

Design Engineer II

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join our world-class SSG IP Integration and QA engineering team as we push the
boundaries of chip design. As an IP Integration & QA Engineer, you'll be at the
intersection of cutting-edge technology and quality excellence, working on
projects that power tomorrow's devices.
This is more than just another engineering role—it's your gateway to mastering advanced semiconductor design while contributing to products used by millions worldwide. You'll collaborate with brilliant minds across global R&D teams, learn from industry veterans, and gain hands-on experience with emerging AI-driven design automation.

Core Responsibility:

Integrate & Build
Work with RTL designs to integrate PHYs and controllers into robust subsystems
Ensure Quality
Validate customer configurations through comprehensive verification regressions
Maintain Excellence
Support design quality checks across LINT, RDC, CDC, and consistency validation
Automate Smartly
Develop scripts and automation workflows to streamline QA processes
Solve Problems
Debug verification issues and collaborate with IP providers on resolution
Embrace Innovation
Learn and apply cutting-edge Agentic AI tools in modern EDA workflows

Technical Foundation
Required:
Education: Bachelor's degree in Electronics Engineering, Computer Engineering, or related field
Experience:
2+ years in digital design or verification
RTL Knowledge:
Solid understanding of Verilog/SystemVerilog
ASIC Fundamentals:
Familiarity with design flows including RTL, simulation, synthesis,and timing
Scripting Skills:
Working proficiency in Python, Perl, TCL, or Shell scripting
Tool Aptitude:
Quick learner with ability to master new EDA tools and methodologies
Bonus Points:
✓ Exposure to Power Flow concepts (UPF/CPF)
✓ Experience with DFT, CDC, LEC, or formal verification tools
✓ Knowledge of DDR protocols (DDR3/DDR4/DDR5) or analog design flows
✓ Familiarity with version control systems (Git, SVN)
✓ Prior internships or academic projects in VLSI/ASIC domain

We’re doing work that matters. Help us solve what others can’t.

Experience Level

Mid Level