Lead Design for Testability Engineer - Silicon

Design for Testability Engineer Lead, Silicon

Minimum qualifications:

• Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
• 8 years of experience in DFT/DFD flows and methodologies.
• Experience with DFT EDA Tool Tessent/Genus/FC/Simvision, etc.
• Experience with scan insertion, ATPG, gate level simulations and silicon debug, low power designs, BIST, JTAG, IJTAG tools and flow.

Preferred qualifications:

• Experience with industry DFT, MBIST, and ATPG tools.
  
• Knowledge of high performance design DFT techniques like SSN, HighBandwidth IJTAG.
• Understanding of the end to end flows (e.g., design, verification, DFT and PD phases in a SOC cycle).
• Proficiency with IJTAG ICL, PDL terminology, ICL extraction, ICL modeling with Siemens Tessent Tool.
• Proficiency with a scripting language such as Perl or Python.

Proficiency with a scripting language such as Perl or Python.Proficiency with a scripting language such as Perl or Python.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Collaborate with a team of DFT engineers, working closely with RTL, Physical Design, SoC DFT, and Product Engineering teams.
• Architect SoC and Subsystem Memory Built-In Self-Test (MBIST) structures across multiple voltage and power domains.
• Drive cross-functional design efforts regarding memory repair methodology and system-level integration.
• Own Gate-Level Simulation (GLS) verification and debug sign-off, ensuring total functional and timing coverage.
• Develop MBIST TbGen, pattern generation, and DFT simulation flows, including scripting to automate and optimize the DFT environment.

Experience Level

Senior Level