Design Quality and Reliability Engineer

Design Quality and Reliability Engineer

Job Details:

Job Description: 

·       In this position you will work in a group of pre-Silicon design Quality and Reliability Engineers (QRE), supporting development of CPU and Hard IPs on the most advanced Intel processes.

·       You will be responsible for pre-Silicon verification and execution of simulations in the design phase as well as developing new design methods, flows and tools for VLSI circuit IP and SoC projects.

·       Primary responsibilities are to collaborate with Hard IP and SoC design teams, perform quality audits in the design phase, risk assessments on pre-silicon design reliability and analysis of physical design performance verification (PV) as well as reliability verification (RV) results.

·       Key tasks include pre-silicon design modeling and correct-by-construction design simulation verifications to mitigate circuit marginalities in Device Aging, Interconnect Reliability (Electromigration), Electro Static Discharge (ESD), Latch-Up (LU), Soft Error Reliability (SER) as well as design/package interactions.

·       Other tasks include program management and technical guidance to junior team members. An important aspect of this role is to assess risks associated with design process marginalities and drive resolutions with partners from design architecture and manufacturing teams.

Qualifications:

o   Bachelors / Masters / PhD in Electronics Engineering, Physics or Material Science with 3+ years of relevant experience in circuit simulation, PV, RV and Physical Design.

o   Strong skills in device physics and circuit operations along with technical problem solving, communication and data analysis.

o   Knowledge in analog and digital circuit design methodologies (timing, noise, physical design, circuit design, mask design and layout).

o   Understanding of optimizations and trade-offs to achieve better performance, power, reliability.

o   Experiences in overall VLSI design flow, technology development and device physics are a plus.

o   Design knowledge in the areas of device aging, Interconnect Reliability and ESD-LU is a plus.

o   Experience in programming using scripting languages such as Python or Perl is a plus.

o   Excellent communication and presentation skills.

o   Good written and spoken English.

o   Ability to effectively work in a multi-site team environment.

o   Well organized, with the ability to effectively manage multiple tasks.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

Silicon and Platform Engineering Group (SPE): Deliver breakthrough silicon and platform solutions that deliver industry-leading products today while also defining the next generation of computing experiences.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Experience Level

Mid Level