Senior Design Verification Engineer

Design Verification Engineer III

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with SystemVerilog (SV) and Universal Verification Methodology (UVM).
• 4 years of experience with processor micro-architecture (pipelines, caches, and memory consistency) and common bus protocols (AHB, AXI, or APB).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science.
• Experience with Formal Verification.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.

Responsibilities

• Verify Intellectual Property (IP) blocks and processor-based subsystems using Universal Verification Methodology (UVM) based constrained random environments.
• Work cross-functionally to debug failures and verify the functional correctness of the design.
• Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use.

Experience Level

Senior Level