DFT Design Engineer

DFT Design Engineer -Memory Team

As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. 

Roles and Responsibilities

• Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies
• Executed scan & MBIST insertion, ATPG and verification at full chip level
• Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts
• Generate, review and validate DFT constraints to achieve timing closure of high speed design
• Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations) 
• Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification
• Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests
• Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved
• Understanding of Power Estimation/Management for DFT modes is preferred
• Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples
• Strong written and oral communication skills

Experience – 5+ Years

Qualifications

• B.Tech/B.E/M.Tech/M.E