Digital Design Engineer, RTL

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 3 years of experience with multiple SoCs with Silicon success.
• Experience with chip design flow.

Preferred qualifications:

• Experience in micro-architecture and coding in one or more of the following areas: memory compression, interconnects, coherence, cache.
• Knowledge of ARM based SoC, Debug (coresight).
• Understanding of cross-domain involving domain validation, design for testing, physical design, and software.
• Understanding of Verilog or System Verilog language.
• Proficiency with ASIC design methodologies for front quality checks like; Lint, CDC/RDC, Synthesis, design for testing, ATPG/Memory BIST, UPF, and Low Power Optimization/Estimation.

Responsibilities

• Work on both the IP design and integration activities including: plan tasks, support, hold code and design reviews, contribute on sub-system/chip-level integration.
• Interact closely with the architecture team and develop implementation strategies to meet quality, schedule, and power performance area for IPs.
• Interact with the subsystem team and plan System-on-Chip (SoC) milestones, plan quality checks as part of SoC milestones (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.).
• Work with cross-functional teams of verification, design for test, physical design, emulation, and software to make design decisions and represent project status throughout the development process.

About the job

The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.