GPU Physical Design Engineer

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

The Qualcomm Graphics Silicon Team in Bangalore is seeking a Physical Design Lead. Our power-efficient GPU solutions are fundamental to enabling exciting new markets such as Virtual Reality (VR), Internet of Things (IoT), Artificial Intelligence (AI), drones, and autonomous driving. We are looking for a talented Physical Design Lead to create world-class GPU products that deliver high-performance graphics and computing with low power consumption. The Graphics Silicon team in Bangalore is part of a global team responsible for developing and delivering GPU solutions that set industry benchmarks. Qualcomm boasts a strong portfolio of GPU cores, providing engineers with the opportunity to work with a world-class engineering team that leads the industry through innovation and disciplined execution.
Role and Responsibilities:
As a Graphics Physical Design Lead, you will be responsible for innovating, developing, and implementing GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and the delivery of complex, high-speed, low-power GPU cores. Your tasks will include the development and enablement of low-power implementation methods, customized place, and route (P&R) to achieve area optimization and performance goals. Additional responsibilities include:
Understanding functional and test (DFT) mode constraints for place and route.
Floor planning, power planning, IR drop analysis, and placement.
Multi-mode and multi-corner (MMMC) clock tree synthesis, routing, timing optimization, and closure.
RC extraction, signal integrity, crosstalk noise and delay analysis.
Debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging, and fixing violations, and formal verification.
Qualifications:
The ideal candidate should possess deep knowledge of scripting and software languages, including PERL/TCL, Linux/Unix shell, and C. This individual will design, verify, and deliver complex Physical Design solutions from netlist and timing constraints to the final product.

Minimum Qualifications:
Bachelor's or Master’s degree in Electrical or Electronic Engineering from a reputed institution.
Over 12 years of experience in Physical Design and Implementation.
Minimum Requirements:
Expertise in physical implementation activities for high-performance GPU cores, including floor-planning, place and route, clock tree synthesis (CTS), formal verification, physical verification (DRC/LVS), power distribution network (PDN), timing closure, and power optimization.
Proficient in physical design implementation of performance, power, and area (PPA) critical cores, with the ability to make informed PPA trade-off decisions.
Strong expertise in achieving timing convergence for high-frequency, data-path intensive cores and advanced static timing analysis (STA) concepts.
Well-versed in block-level place and route (PnR) convergence using Synopsys ICC2 or Cadence Innovus, and timing convergence using PTSI or Tempus in the latest technology nodes.
Comprehensive understanding of clocking architecture.
Ability to collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, and physical design.
Proficient in Tcl and Perl scripting.
Experience working as part of a larger team, meeting project milestones and deadlines, and handling technical deliverables with a small team of engineers.
Strong problem-solving skills and excellent communication skills.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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