Mixed Signal Design Verification Engineer

Mixed Signal Design Verification Engineer

Job Details:

Job Description: 

Performs functional verification of digital and mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the pre-silicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Mentor the Junior engineers and get results done through them.

Qualifications:

The candidate should possess a BE/B.Tech with 12 year experience OR ME/M.Tech degree with 10 years of relevant industry experience. Candidate should have worked on IP verification using Verilog/System Verilog.
Experience in the following areas/skills are desired:
UVM coding
System Verilog
Excellent knowledge on DDR4/DDR5/LP5/LP6 protocol
Expertise in comprehensive verification of DDR IP
Low-power design using UPF and clock gating
Multiple clock domain design
State machine design
Simulation and debug experience using VCS/Verdi
Checker development, Verification environment development.
Integrating BFM/Checkers
Subsystem to SoC Integration
Writing Test plans and testcases
Coding Coverage and assertions.
Exposure to Mixed signal verification
Exposure to GLS verification.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.