R&D Engineering- Sr Staff Engineer - Design Verification/ VIP Verification Engineers

You Are:

As an experienced Verification Engineer, you are passionate about ensuring the highest standards of quality in complex system designs. With over a decade of experience in IP verification, you bring a deep understanding of verification methodologies and the intricacies of hardware design. You are adept at designing self-checking test benches using modern verification techniques, and you excel in developing verification components such as bus functional models, monitors, and behavioral models. Your expertise in implementing functional coverage and assertions using System Verilog is unmatched. You are a problem-solver who thrives in debugging simulation failures and analyzing functional coverage results. Your strong Verilog coding skills, combined with your prowess in C/C++ or Python scripting, make you a valuable asset to any team. You are a fast learner, comfortable and confident interacting with architects, and you possess excellent written and verbal communication skills.

What You’ll Be Doing:

• Designing and implementing self-checking test benches using modern verification techniques.
• Developing verification components such as bus functional models, monitors, and behavioral models.
• Implementing functional coverage and assertions using System Verilog.
• Creating and executing test and functional coverage plans based on device specifications.
• Analyzing and debugging simulation failures to identify root causes.
• Evaluating functional coverage results to ensure thorough verification.

The Impact You Will Have:

• Ensuring the highest quality of IP verification, contributing to the reliability and performance of cutting-edge technology.
• Enhancing the efficiency of the verification process through innovative test bench designs.
• Contributing to the development of high-performance silicon chips that power a wide range of applications.
• Supporting the continuous improvement of verification methodologies and best practices.
• Collaborating with cross-functional teams to achieve project milestones and deliverables.
• Mentoring and guiding junior engineers, fostering a culture of knowledge sharing and continuous learning.

What You’ll Need:

• B.Tech/M.Tech with a minimum of 10+ years’ experience in IP verification.
• Proficiency in Verilog and System Verilog for test bench development.
• Experience with object-oriented verification languages like SV, UVM.
• Strong debugging skills and experience with industry-standard simulation tools such as Synopsys VCS, Verdi.
• Knowledge of FPGA architectures and experience in DDR IP verification.

Who You Are:

• A fast learner with the ability to quickly adapt to new technologies and methodologies.
• An excellent communicator with strong written and verbal communication skills.
• A team player who collaborates effectively with cross-functional teams.
• An analytical thinker with strong problem-solving skills.
• A mentor who enjoys sharing knowledge and guiding junior engineers.