RTL Design Engineer, Security

Minimum qualifications:

• 5 years of experience in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC).
  
• Experience in scripting language such as Perl or Python.
  
• Experience in area, power and performance optimization.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience.
• Experience in design and development of security blocks or crypto blocks.
  

Responsibilities

• Participate in test planning and coverage analysis.
  
• Develop RTL implementations that meet power, performance and area goals.
  
• Participate in synthesis, timing/power closure and Field Programmable Gate Array (FPGA) and silicon bring-up.
  
• Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks.
• Create tools/scripts to automate tasks and track progress.
  
  

About the job

In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes Micro architecture, RTL coding, UPF definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews and closure for high quality and optimized security designs.

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