Senior ASIC RTL Engineer - Subsystem Integration

Senior ASIC RTL Engineer, Subsystem Integration

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience in RTL design using Verilog/System Verilog.
• 8 years of experience in subsystem microarchitecture creation, RTL integration and delivery.
• Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC, VCLP, synthesis).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, or a related field.
• 12 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog.
• Experience in leading subsystem integration and delivery.
• Experience in micro architecting and generating interconnects/Network on Chip (NOC) for subsystems/SOC.
• Proficiency in AMBA (Advanced Microcontroller Bus Architecture) protocol (e.g., AXI/APB/AHB/ACE/CHI).
• Expertise in low power design, power estimation, analysis and optimization.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Collaborate with Architecture teams and define the microarchitecture of complex Subsystems including interface protocols, block diagrams, and data flow.
  
• Develop RTL implementations (verilog/system verilog) and create the required subsystem that meets competitive Power, Performance, and Area (PPA) targets.
• Perform RTL quality checks such as Lint, CDC, RDC, SDC and UPF checks.
• Participate in debugs with the verification team to ensure a functional design. Own power analysis and optimization for the subsystem, ensuring exceptional PPA.
  
• Lead a team of engineers to ensure high quality, on time delivery of subsystems.

Experience Level

Senior Level