Senior Design for Testability Engineer

Senior Engineer - DFT

Purpose:

The Design for Testability (DFT) engineering organization at L&T Semiconductor Technologies (LTSCT) pioneers innovative methods and technologies in the areas of DFT architecture, verification, and post-silicon bring-up of state-of-the-art semiconductor chips, such as System on a Chip (SoCs), developed using the latest semiconductor technology nodes.

Areas of Responsibilities:

· Lead and manage the DFT team to achieve project goals.

· Implement various DFT techniques, including:

• Memory Built-In Self-Test (MBIST) insertion.
• Compressor-based scan chain insertion.
• Boundary Scan (BSCAN) structure insertion compliant with IEEE 1149.1 and 1149.6 standards.
• Logic Built-In Self-Test (BIST) for self-test capability.
• Analog BIST implementation for selected analog blocks, such as PLLs, ADCs, and DACs.
• IO Built-In Self-Test (IOBist) methods for IO structures of SoCs.

·  Conduct DFT simulations and analyze results to ensure comprehensive test coverage and high quality.

·  Debug and resolve DFT-related issues throughout the design process.