Engineering Manager - Silicon Design Verification

Silicon Engineering Manager, Design Verification

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC design verification methodology.
• Experience in leading or managing IP or SS verification teams.
• Experience in UVM based IP and SS/SOC verification.
• Experience with programming in Verilog, SystemVerilog, and Perl/Python.
• Experience with industry-standard EDA tools and methodologies.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 15 years of experience in ASIC design verification methodology.
• Experience in Portable Test and Stimulus Standard (PSS) , Formal or emulation based Simulation Accelerator (SimXL) methodologies.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Lead and manage verification activities for the Subsystems (SS) and SoC.
• Develop all aspects of logic verification infrastructure and methodology for complex mobile SOC IP or SS blocks.
• Collaborate with design teams to ensure seamless integration of verification methodology into the design process.
• Improve verification methodologies to increase efficiency and effectiveness.
• Collaborate with both external and internal CAD teams to develop new verification solutions that can improve the quality and efficiency.

Experience Level

Senior Level