Staff Engineer - ASIC Verification

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

• You are a highly motivated ASIC Digital Design Engineer with a passion for pushing the boundaries of technology.
• With a strong background in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI, you excel in functional verification flows and methodologies, particularly VMM, OVM/UVM, and System Verilog.
• Your expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation sets you apart.
• You possess fundamental knowledge of Analog and Digital mixed signal design, and your scripting skills in TCL/Perl/Python are top-notch.
• You are a team player with excellent communication skills, problem-solving abilities, and interpersonal skills, eager to deliver high-quality RTL and Simulation models to customers and support them through silicon bring-up and debug processes.

What You’ll Be Doing:

• Develop and review the verification test-plan for multi-protocol 112G PHY IP sub-system of Controller/MAC+PCS+PHY.
• Create and optimize the verification environment based on UVM.
• Verify the inter-operability of Controller/MAC, PCS, with PHY of different Tech nodes.
• Execute RTL simulations, Gate Level Simulations, and ensure coverage closure (Functional + Code).
• Deliver high-quality RTL and Simulation models to customers.
• Coordinate between RTL, Analog design, and Tech pub teams.
• Support customers with the integration and bring-up of IP in their simulation environments.
• Develop and deliver SV verification components for customer integration.
• Assist customers with silicon bring-up and debug issues when customer silicon is available.

The Impact You Will Have:

• Ensure the delivery of robust and high-quality verification solutions for Synopsys’ high-performance PHY IPs.
• Drive innovation and efficiency in verification processes, contributing to the advancement of cutting-edge technologies.
• Enhance customer satisfaction through exceptional support and high-quality deliverables.
• Facilitate the seamless integration of Synopsys IPs into customer designs, ensuring successful product launches.
• Contribute to the development of industry-leading verification methodologies and best practices.
• Help maintain Synopsys’ reputation as a leader in chip design and verification solutions.

What You’ll Need:

• B.Tech/M.Tech with 7+ years of relevant experience.
• Proficiency in interface protocols such as Ethernet, PCIe, CXL, JESD, and CPRI.
• Experience with functional verification flow, Verification tools, and methodologies VMM, OVM/UVM, and System Verilog.
• Expertise in Gate Level Simulation with SDF, System Verilog Assertions, and coverage implementation.
• Fundamental knowledge of Analog and Digital mixed signal design.
• Proficiency in scripting and automation using TCL/Perl/Python.
• Excellent debug and diagnostic skills.