Senior Silicon Design Verification Engineer

Staff Silicon Design Verification Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
• 10 years of experience with IP and subsystem verification, particularly with fabric IP and memory controllers.
• 10 years of experience developing UVM (Universal Verification Methodology) testbenches.
• Experience developing verification components using SystemVerilog.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience in low-power design verification.
  
• Experience in formal verification.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

• Verify designs using verification techniques and methodologies.
  
• Work cross-functionally to debug failures and verify the functional correctness of the design.
  
• Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage; ensure documentation is easy to use.
• Lead and manage verification activities for subsystems or SoCs.
• Develop all aspects of logic verification infrastructure and methodology for mobile SoC IP or subsystem blocks.

Experience Level

Senior Level