Senior Digital Verification Engineer

Staff Verification Engineer

General Information

Job Title Staff Verification Engineer Job ID 16178 Country India City Bhubaneswar Date Posted 11-Mar-2026 Job Category Engineering Job Subcategory R&D Engineering Hire Type Employee Remote Eligible No

Descriptions & Requirements

Job Description and Requirements

Staff Digital Verification Engineer

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a passionate and experienced verification engineer, eager to take ownership and drive excellence in IP and SoC-level verification. With 5–8 years of hands-on digital verification experience, you thrive on solving complex challenges and collaborating with cross-functional teams. You possess deep expertise in Verilog, SystemVerilog, and UVM, and are adept at building robust verification environments. Your technical curiosity pushes you to innovate and optimize test strategies, ensuring high-quality silicon delivery. You have a proven track record of developing behavioral models, writing comprehensive test cases, and achieving coverage closure. You are comfortable debugging intricate issues, analyzing waveforms, and leveraging scripting skills in Shell, Makefile, or Python to automate and streamline verification processes. You excel in communication, are detail-oriented, and welcome feedback to continually improve. Your proactive attitude, adaptability, and commitment to continuous learning make you a trusted leader among peers. You are excited by the opportunity to work on PVT sensing IP and to make a tangible impact on next-generation semiconductor products. You value inclusivity, collaboration, and the chance to mentor junior engineers, sharing your knowledge and supporting their growth. If you’re looking for a dynamic environment where your expertise will shape the future of technology, Synopsys is your ideal destination.

What You’ll Be Doing:

• Planning and executing IP/SoC verification using UVM environments, including agents and scoreboards, to ensure comprehensive coverage and robust design validation.
• Developing behavioral models such as SV/TLM stubs, bus functional models (BFMs), checkers, and AMS-friendly models aligned with specifications.
• Writing constrained-random and directed testcases, assertions (SVA), and debugging complex issues using waveforms and logs.
• Driving code and functional coverage to target metrics, maintaining stable regression suites and continuous integration pipelines.
• Running Gate-Level Simulations (GLS) with and without SDF, performing reset, X-propagation, and low-power sanity checks.
• Collaborating closely with Design, DFT, Physical Design, and Firmware teams, and supporting emulation activities (ZeBu) as needed.

The Impact You Will Have:

• Ensuring the delivery of high-quality, reliable PVT sensing IP for integration into advanced SoC designs.
• Reducing time-to-market for critical semiconductor products by streamlining verification processes and driving coverage closure.
• Enhancing product robustness and performance through comprehensive verification and proactive issue resolution.
• Elevating Synopsys’ reputation for innovation and reliability in the semiconductor industry.
• Fostering cross-team collaboration that accelerates product development and enables successful tapeouts.
• Mentoring and empowering junior engineers, contributing to a culture of continuous improvement and technical excellence.

What You’ll Need:

• Strong proficiency in Verilog, SystemVerilog, and UVM for environment development and maintenance.
• Hands-on experience with IP/SoC verification ownership, including test planning, coverage, and regression management.
• Expertise in writing and debugging SystemVerilog Assertions (SVA) and complex testcases.
• Experience with coverage closure (code and functional), waveform analysis, and log triage.
• Familiarity with Shell scripting, Makefiles, and Python for automation and utility development.

Who You Are:

• Analytical thinker with excellent problem-solving skills.
• Effective communicator, able to collaborate across diverse teams.
• Detail-oriented and quality-focused, with a passion for technical excellence.
• Proactive and adaptable, eager to learn and take on new challenges.
• Inclusive team player who values mentorship and knowledge sharing.

The Team You’ll Be A Part Of:

You’ll join a high-performing verification team specializing in PVT sensing IP development for next-generation SoCs. The team is dedicated to delivering robust, scalable, and innovative solutions, working in close partnership with design, DFT, PD, and firmware groups. You’ll collaborate with experts who value technical depth, open communication, and continuous improvement, contributing to Synopsys’ leadership in the semiconductor industry.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

Experience Level

Senior Level