Associate Design for Test (DFT) Engineer

Associate Engineer - DFT

Position:

Associate Engineer - DFT

Job Description:

• 5+ years of hands-on experience in Scan insertion at block level and/or MBIST insertion at block level
• ATPG and Pattern verification at Block level
• Debug and enhance DFT architecture and setup DFT flow
• Debug iJTAG and IEEE 1500 core wrapper-based architecture
• Pattern diagnosis and debug the ATE pattern failures
• Very good debugging skills
• Boundary Scan implementation
• Create and debug DFT modes timing constraints
• Scripting for flow automation
• Should have worked on below Tools:

Synopsys tools: DFTMAX, TetraMAX, VCS, Verdi and PT

OR Cadence tools: Genus and Modus, NC-SIM/Irun, Sim-Vision, LEC

OR Mentor Graphics tools: Tessent tool chain, TestKompress, Questa

• Ability to work independently on DFT flow enhancement, Full chip/Block level Scan, MBIST. Work closely with DFT lead to solve complex technical issues
• Technically sound & good team player
• Familiarity with ATE will be plus

Worked on at least one Fullchip project is desired

Qualifications:

 B.E., B.TECH., M.E., M. TECH

Location:

IN-UP-Noida, India-World Trade Tower (eInfochips)

Time Type:

Full time

Job Category:

Engineering Services

Experience Level

Mid Level