GPU Static Timing Analysis Engineer

GPU STA/Timing Engineer (Lead/Staff)

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

Qualcomm GPU team is actively seeking candidates for several STA/Timing Sign-off positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry. Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution.  

As a STA engineer you will innovate, develop, and implement chips and cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Job Responsibilities include:

• Participate in the development of ASICs, with emphasis in Constraint development, Synthesis, Static Timing Analysis (STA), Power Estimation/Optimization and driving clock tree synthesis.

• Create design of experiments and do detail PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward.

• Work closely with RTL design, DFT, PD Implementation, Power teams to optimize Performance, Power and Area (PPA) for best PPA

• Proficient in constraint generation and validation.

• Develop Rapid Physical Synthesis Convergence Methodologies and Automation for optimal PPA.

• Help all team members in resolving their technical queries and keep project on track.

• Develop new flow and methodologies to keep improving QOR.

Minimum Qualifications

• Bachelor's/master’s degree in electrical and Electronics Engineering or related field from reputed Univ

• 5+ years IC Design experience or related work experience in leading block level or chip level Timing closure & Physical Design activities.

Minimum Requirements:

• Experience in Physical Synthesis and static timing analysis

• Well versed with the Block level and Interface timing closure (STA) methodologies, ECO generation and predictable convergence.

• Should be able work in close collaboration with design, DFT and PD teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.

• Should have good exposure to High frequency Datapath intensive Cores with multi voltage design convergence.

• Should be completely hands on in Primetime/Tempus.

• Good understanding of clocking architecture.

• Circuit level comprehension of timing critical paths in the design; Understanding of deep sub-micron design problems and solutions (Skew analysis, clock divergence, signal integrity etc.)

• Full exposure to all aspects of design flows like floor-planning, placement, CTS, routing, crosstalk avoidance.

• Well versed with Tcl/Perl scripting; willing to handle technical deliverables with a small team of engineers.

• Strong problem-solving skills and communication skills.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

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