Senior Design Verification Engineer

Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

• BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer.

• 7+ years of Design Verification experience with SV/UVM

• Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.

• Design Verification experience verifying complex designs and leading projects from concept to verification closure.

• Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required.

Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage.

We’re doing work that matters. Help us solve what others can’t.

Experience Level

Senior Level