Jobs

Engineering - Hardware & Networks

Anywhere in India

Agra

Ahmedabad

Ahmednagar

Ajmer

Aligarh

Amritsar

Asansol

Aurangabad

Bareilly

Belagavi

Bengaluru

Bhavnagar

Bhilai

Bhopal

Bhubaneswar

Bikaner

Chandigarh

Chennai

Coimbatore

Cuttack

Dehradun

Delhi-NCR

Dhanbad

Gorakhpur

Guntur

Guwahati

Gwalior

Hubli

Hyderabad

Indore

Jabalpur

Jaipur

Jalandhar

Jamnagar

Jamshedpur

Jodhpur

Kannur

Kanpur

Kochi

Kolhapur

Kolkata

Kota

Lucknow

Ludhiana

Madurai

Malappuram

Mangalore

Meerut

Mumbai

Mysuru

Nagpur

Nashik

Panipat

Patna

Prayagraj

Puducherry

Pune

Raipur

Rajkot

Ranchi

Saharanpur

Salem

Solapur

Surat

Thiruvananthapuram

Trichy

Udaipur

Ujjain

Vadodara

Varanasi

Vijayawada

Visakhapatnam

Warangal

Admin / Back Office / Computer Operator

Advertising / Communication

Aviation & Aerospace

Banking / Insurance / Financial Services

Beauty, Fitness & Personal Care

Construction & Site Engineering

Consulting

Content, Editorial & Journalism

CSR & Social Service

Customer Support

Data Science & Analytics

Delivery / Driver / Logistics

Domestic Worker

Energy & Mining

Environment Health & Safety

Facility Management

Finance & Accounting

Healthcare / Doctor / Hospital Staff

Human Resources

IT & Information Security

Legal & Regulatory

Maintenance Services

Marketing / Brand / Digital Marketing

Media Production & Entertainment

Operations

Production / Manufacturing / Engineering

Product Management

Project & Program Management

Purchase & Supply Chain

Quality Assurance

Research & Development

Restaurant / Hospitality / Tourism

Retail & eCommerce

Risk Management & Compliance

Sales & BD

Security Services

Shipping & Maritime

Software Engineering

Strategic & Top Management

Tailoring, Apparel & Home Furnishing

Teaching & Training

UX, Design & Architecture

Popular Job Localities

Popular Job Companies

Popular Job Departments

Jobs in Top Cities

Popular Job Type

Start Hiring

Silicon Validation Engineer <ul><li>Looking for engineers with strong skills in&nbsp;C, Python, post-silicon validation,&nbsp;x86 architecture, and system-level debugging.</li><li>Experience:4-10 Years</li></ul> Interested candidates, please share your resume at: <a rel="noopener noreferrer" href="\&quot;mailto:PrasadKaruturi@Mirafra.com\&quot;" target="_blank">PrasadKaruturi@Mirafra.com</a>.

Mirafra Software Technologies Pvt Ltd

Testing Engineer

DFT Design Engineer - Foundry Team As one of the largest R&amp;D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.&nbsp; Roles and Responsibilities5+ years of experience in full chip DFT architecture, implementation, timing closure and post silicon validation. Expertise required in the following areas:<ul><li>Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modes</li><li>MBIST architecture planning, repair architectures, insertion, verification</li><li>Analog and mixed signal IP testing architecture and verification including IPs such as PLLs, PHYs</li><li>Timing closure of scan, MBIST and other test modes, writing SDCs, understanding of timing exceptions wherever required, debugging timing issues with PD team</li><li>Timing GLS, debug of fails in simulations</li><li>Post silicon validation, interpretation of tester results, debugging IR drop issues, diagnostics of silicon failures</li><li>Understanding of JTAG operation and debug required. Understanding of iJTAG protocol desirable</li><li>Understanding of functional test cases, IO testing, testing of ARM processor cores</li><li>Ability to lead a team across all aspects of DFT, interact with RTL, physical design teams for DFT implementation, anticipate risks, plan project timelines and milestones</li></ul> Experience – 5+ Years Qualifications<ul><li>B.Tech/B.E/M.Tech/M.E</li></ul>

Samsung India Electronics Pvt Ltd 

Electronic Engineer

DFT Design Engineer -Memory Team As one of the largest R&amp;D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.&nbsp; Roles and Responsibilities<ul><li>Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies</li><li>Executed scan &amp; MBIST insertion, ATPG and verification at full chip level</li><li>Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts</li><li>Generate, review and validate DFT constraints to achieve timing closure of high speed design</li><li>Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations)&nbsp;</li><li>Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification</li><li>Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests</li><li>Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved</li><li>Understanding of Power Estimation/Management for DFT modes is preferred</li><li>Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples</li><li>Strong written and oral communication skills</li></ul> Experience – 5+ Years Qualifications<ul><li>B.Tech/B.E/M.Tech/M.E</li></ul>

CATIA CAA Senior Software Engineer Must to have skills<ul><li>CATIAV5 Functional Knowledge(part/Assembly/Generative shape Design)&nbsp;</li><li>CATIA V5 CAA</li><li>C++, Data structures and Design Patterns&nbsp;</li><li>C# and .Net</li><li>Geometry Concepts</li><li>Git Source code Management</li><li>Agile Tools-JIRA/VersionOne/confluence</li></ul>&nbsp;Good to have skills<ul><li>3DX EKL/VB</li><li>PLM Knowledge (PASS/VPM)</li><li>Ability to create clear and detailed technical documentation for the developed applications and customizations.</li></ul>&nbsp;Other skills<ul><li>Strong analytical and problem-solving abilities to troubleshoot and resolve issues within the CATIA environment.</li><li>Good communication skills for interacting with stakeholders, gathering requirements, and collaborating with team members.</li></ul>&nbsp;&nbsp;Responsibilities:<ul><li>Collaborating with and across Agile teams to design, develop, test, implement, and support technical solutions</li><li>Working as part of a multi-functional agile team including business experts, data analysts, architects</li><li>Being involved in all parts of the product life cycle: idea generation, design, prototyping, planning, development, test, deployment and operations</li><li>Create clean, efficient, and well-documented code following coding standards.</li><li>Create and maintain proper documentation throughout the software development phase.</li><li>Support with technical assistance and serve as an application specialist.</li><li>Advising on necessary software and infrastructure changes and evolution.</li></ul> Total Experience Expected: 02-04 years Qualifications<ul><li>B.Tech</li></ul>

Sopra Steria India Limited

Senior Software Engineer

STA Engineer Skills requried:• In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and lower technology nodes.• Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.• Must have hands-on experience on PnR Suite from Synopsys/Cadence (Innovus, ICC2)• Strong experience on Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).• Understanding the practical application of methodologies and Physical Design Tools, Flow Automation and Improvements.• Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques. Experience:&nbsp;3-8 Years

Modernize Chip Solutions

Associate Engineer

ISP Silicon Validation Engineer<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Computer Science, Electrical Engineering or equivalent practical experience. </li><li>3 years of experience with Computer Architecture.</li><li>Experience with C/C++, Python or Bash.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Master's degree in Computer Science, Electrical Engineering or equivalent practical experience.</li><li>Experience with software development tools, version control, compilers, and build tools.</li><li>Experience with hardware accelerators for camera multimedia systems.</li></ul><h4>About the job</h4>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.<h4>Responsibilities</h4><ul><li>Develop, and execute software tests to validate ISP blocks and integration.</li><li>Read hardware specifications, identify and develop test cases to run on Field-programmable Gate Array (FPGA) emulation and silicon.</li><li>Develop software test methodologies.</li><li>Support volume production through screening and characterization tests.</li><li>Support power measurements, correlation and debug.</li></ul><h4>Experience Level</h4>Mid Level

Google India Pvt Ltd

VP- Engineering Job Summary:We are looking for experienced VP- Engineering to provide sound technical leadership in all aspectsof our business. You will communicate with employees, clients, and customers to ensure ourcompany’s technologies are used appropriately.Strategic thinking and strong business acumen are essential in this role. We expect you to be wellversed in current technological trends and familiar with a variety of business concepts. If you are also an excellent communicator and public speaker Responsibilities:• Develop technical aspects of the company’s strategy to ensure alignment with its business goals• Discover and implement new technologies that yield competitive advantage• Help departments use technology profitably• Supervise system infrastructure to ensure functionality and efficiency• Build quality assurance and data protection processes Monitor KPIs and IT budgets to assess technological performance• Use stakeholders’ feedback to inform necessary improvements and adjustments to technology• Communicate technology strategy to partners and investors Requirements:• Proven experience in technology or similar leadership role• Knowledge of technological trends to build strategy• Understanding of budgets and business-planning• Ability to conduct technological analyses and research• Excellent communication skills• Leadership and organizational abilities• Strategic thinking• Problem-solving aptitude• B.Sc/B.Tech in Computer Science or a related field; MBA or other relevant graduate degree is a plus Experience:<ul><li>8+ years&nbsp;</li></ul>

BioQube

Senior Project Manager

Hardware Design Engineer We are looking for talented Hardware Design Engineer to join our team. Experience: 4-9 YearsDescription• Experience in complete hardware design life cycle• Experince in schematic and bom generatin layout co-ordination.• Strong Knowledge of ASPICE for Hardware Engineering (HWE),• Understand EMI/EMC Standards• Knowledge of Standard like Functional Safety (Part-5 Hardware) ISO26262

L&T Technology Services Ltd

Hardware Engineer

Scada - Ignition Engineer We're hiring below position: Position: Scada - Ignition Engineer&nbsp;Experience: 4 to 6 years If you're interested, please share your profile.

Capgemini

Electrical / Electronics Engineer

Design for Test Engineer Job DescriptionWe are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with a minimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities<ul><li>Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans.</li><li>Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy.</li><li>Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&amp;R IP blocks for Scan, MBIST and other test interfaces.</li><li>Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing.</li><li>Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet.</li><li>Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs.</li><li>Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations.</li><li>Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types.</li><li>Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues.</li><li>Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs.</li><li>Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting.</li><li>Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow.</li><li>Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory.</li><li>Knowledge of LogicBIST with Test point insertion, X-blocking.</li><li>Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements.</li><li>Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug.</li><li>Ability to perform volume diagnostics on the parts to isolate and improve the patterns.</li></ul> Requirements<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design for Test.</li><li>Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows.</li><li>Prior experience working on IP level and SOC level DFT projects.</li><li>Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc.</li><li>Worked in full chip design or complex IP delivery in the area of DFT.</li><li>Experience in post silicon debug, diagnosis and yield enhancements is a plus.</li></ul>

AI Resume builder

AI Resume checker

AI Cover letter generator

Blog

Engineering - Hardware & Networks Jobs - 1546 Verified Vacancies

Testing Engineer

Electronic Engineer

Electronic Engineer

Senior Software Engineer

Associate Engineer

Testing Engineer

Senior Project Manager

Hardware Engineer

Electrical / Electronics Engineer

Senior Test Engineer

Know more about Engineering Hardware Networks Jobs In Ernakulam