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Linux Kernel Engineer Skills - Linux Kernel, OS DevelopmentExperience - 4–8 years Interested candidates can share their profiles at: <a rel=\"noopener noreferrer\" href=\"https://retool.infra.apna.co/%22https://retool.infra.apna.co/%22mailto:gopi.c@acesoftlabs.com/%22/%22\" target=\"_blank\">gopi.c@acesoftlabs.com</a>

Acesoft Labs India Pvt Ltd

Linux Engineer

Engineering ExecutivePOSITION SUMMARY Install, maintain, perform preventative maintenance on, and recommend replacement of tools, appliances, and equipment. Calibrate all controls, gauges, meters, etc. Identify, locate, and operate all shut-off valves. Order, mark, and stock parts and supplies as needed. Maintain inventory and purchase orders log. Inspect tools, equipment, or machines. Enter and locate work-related information using computers. Operate power lift. Assist management in hiring, training, scheduling, evaluating, counseling, disciplining, and motivating and coaching employees; and serve as a role model. Follow all company and safety and security policies and procedures; report maintenance problems, safety hazards, accidents, or injuries; complete safety training and certifications; and properly store flammable materials. Ensure uniform and personal appearance are clean and professional. Anticipate and address guests’ service needs. Speak with others using clear and professional language and prepare and review written documents accurately and completely. Develop and maintain positive working relationships with others and listen and respond appropriately to the concerns of other employees. Ensure adherence to quality expectations and standards, and identify, recommend, develop, and implement new ways to increase organizational efficiency, productivity, quality, safety, and/or cost-savings. Move, lift, carry, push, pull, and place objects weighing less than or equal to 75 pounds without assistance. Move up and down stairs, service ramps, sloping, uneven, or slippery surfaces, and/or ladders. Reach overhead and below the knees, including bending, twisting, pulling, and stooping. Grasp, turn, and manipulate objects of varying size and weight. Stand, sit, or walk for an extended period of time. Perform other reasonable job duties as requested by Supervisors. PREFERRED QUALIFICATIONS Education: Technical, Trade, or Vocational School Degree.Related Work Experience: 4 to 6 years of related work experience.Supervisory Experience: No supervisory experience.  REQUIRED QUALIFICATIONSLicense or Certification: Valid Driver’s License  


  

At Marriott International, we are dedicated to being an equal opportunity employer, welcoming all and providing access to opportunity. We actively foster an environment where the unique backgrounds of our associates are valued and celebrated. Our greatest strength lies in the rich blend of culture, talent, and experiences of our associates. We are committed to non-discrimination on any protected basis, including disability, veteran status, or other basis protected by applicable law.<h4>Experience Level</h4>Executive Level

Marriott Hotels India

Engineering Manager

Associate Electronics RF Design and Analysis EngineerAssociate Electronics RF Design and Analysis EngineerCompany:Boeing India Private LimitedOverview As a leading global aerospace company, Boeing develops, manufactures and services commercial airplanes, defense products and space systems for customers in more than 150 countries. As a top U.S. exporter, the company leverages the talents of a global supplier base to advance economic opportunity, sustainability and community impact. Boeing’s team is committed to innovating for the future, leading with sustainability, and cultivating a culture based on the company’s core values of safety, quality and integrity. Technology for today and tomorrowThe Boeing India Engineering &amp; Technology Center (BIETC) is a 5500+ engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&amp;D, innovation, and high-quality engineering work in global markets, and leverage new-age technologies such as AI/ML, IIoT, Cloud, Model-Based Engineering, and Additive Manufacturing, shaping the future of aerospace. People-driven cultureAt Boeing, we believe creativity and innovation thrives when every employee is trusted, empowered, and has the flexibility to choose, grow, learn, and explore. We offer variable arrangements depending upon business and customer needs, and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration, frequent team engagements, and face-to-face meetings bring together different perspectives and thoughts – enabling every voice to be heard and every perspective to be respected.  No matter where or how our teammates work, we are committed to positively shaping people’s careers and being thoughtful about employee wellbeing.With us, you can create and contribute to what matters most in your career, community, country, and world. Join us in powering the progress of global aerospace. Position Overview Boeing India Engineering has an immediate opening for an Associate Electronics RF Design and Analysis Engineer to work in areas of RF design. This position offers a unique opportunity to work complex technical challenges in support of safety operation and return to service. This role will be based out of Bangalore, India. Position Responsibilities:<ul><li>Responsible for RF and mixed signal designs.</li><li>Design and simulate RF circuits for cellular modules including LNAs, filters, Diplexers, switching and matching networks.</li><li>Perform testing and validation of RF components and systems - RF amplifiers, filters, and antennas - to validate performance against specifications.</li><li>Perform RF validation, tuning, and debugging using tools such as VNA, spectrum analyzers, and signal generators</li><li>Perform simulation of filters and antenna synthesis using tools like Ansys HFSS</li><li>Perform circuit design, requirements and interface definition and design verification.</li><li>Design to meet EMI/EMC, safety and environmental compliance.</li><li>Develop and optimize RF systems supporting Wifi,4G LTE and 5G.</li><li>Execute testing of designs in Labs for functional, performance and stress environments apart from system integration  </li></ul>Basic Qualifications (Required Skills and Experience)<ul><li>Bachelor’s or Master’s Degree is required as a basic qualification in Electronics and Communication Engineering with 4 to 8 years of relevant experience. </li></ul>Preferred Qualifications (Desired Skills/Experience):<ul><li>Candidate should have experience in RF Design integration capabilities for Wireless communications and 5G integration</li><li>Candidate should have strong experience in high-speed design clocking, Ethernet/Serdes/MIPI designs</li><li>Candidate should have strong experience in knowledge of using simulation tools like SABER RD and creating simulation models with MATLAB and SABER</li><li>Candidate should have experience with Power Integrity analysis, Hyperlynx SI and Mentor suite of eCAD tools</li><li>Candidate should have basic knowledge of cellular and Wi-Fi standards</li></ul>Relocation:<ul><li>This position does offer relocation within INDIA.</li></ul>Language Requirements:Not ApplicableEducation:Bachelor's Degree or EquivalentRelocation:This position offers relocation based on candidate eligibility.Security Clearance:This position does not require a Security Clearance.Visa Sponsorship:Employer will not sponsor applicants for employment visa status.Contingent Upon Award ProgramThis position is not contingent upon program awardShift:Not a Shift Worker (India)<h4>Experience Level</h4>Mid Level

Boeing India Pvt Ltd

Electronic Engineer

Lead Product Engineer Experience: 4-6 Years&nbsp; Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.&nbsp;Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage<ul><li>The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.</li><li>Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.</li><li>The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success</li><li>Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests</li><li>You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.</li></ul> Experience and Technical Skills required:<ul><li>Candidate will be primarily involved in STA job role. That include his involvement in the development and deployment of state of the art signoff tool (Tempus). Candidate should be familiar with STA and Basic ECO features.</li><li>Job will also involve writing specification for tool enhancement and close working with RD to help tool mature/develop with latest features and also per customer’s requirement.</li><li>Need passionate candidate and who is excellent team player.</li><li>B.E/BTech/ME/MTech. in EE/ECE/CS</li></ul>

Cadence Design Systems India Pvt Ltd

Senior Product Manager

Chief EngineerOrganization: At CommBank, we never lose sight of the role we play in other people’s financial wellbeing. Our focus is to help people and businesses move forward to progress. To make the right financial decisions and achieve their dreams, targets, and aspirations. Regardless of where you work within our organisation, your initiative, talent, ideas, and energy all contribute to the impact that we can make with our work. Together we can achieve great things.Job Title: Chief EngineerLocation: BangaloreBusiness &amp; Team:Business Banking Technology (BBT) we have a vision of becoming the leading business bank, powered by the next horizon of technology. We’re delivering on this by working hand-in-hand with our business colleagues to jointly solve problems with customer centricity and technical innovation, cultivating a world-class team of empowered people, and building technology solutions for the future. We put the customer at the center of everything we do and measure our performance against the groups’ external customer satisfaction measures.The Business Banking Technology team within the Technology function manages the end-to-end technology needs for Business Banking (BB) within the CBA Group. Our team is composed of engineers and technology leaders, who bring in the right mix of skills to enable this transformation. We also work very closely with our business and operations colleagues to support these services which are critical to the Australian and Global economy. Working as part of the Payments Senior Leadership team, you will be accountable for prioritizing, coordinating, and leading the execution of technical platform delivery and service management across the BB domain.   Impact &amp; Contribution:<ul><li>This position will be responsible to work with a team of engineers across Payments Technology and partner with stakeholders to build, design and deliver solutions.</li><li>As the Chief Engineer, you will be responsible for leading a large multi-disciplinary function responsible for defining, designing and building the highest-quality re-usable framework for Payments Technology.</li><li>Define the capability uplift approach for the Chapter Area and drives uplift, in partnership with the Practice and peers (where applicable) and in line with industry. As important as ensuring quality outcomes, your role is focused on continually refining implementation standards, accelerating delivery through process improvements and building a world-class team culture.</li></ul>Reporting Lines:<ul><li>Direct line reporting into the Executive Manager, Payments Technology</li><li>Functional (dotted line) reporting into the General Manager, Payments Technology</li></ul>Roles &amp; Responsibilities:<ul><li>Chief Engineer plays a pivotal role to deliver on Payments Technology purpose through quality execution and delivery.  </li><li>Leverage metrics and data to inform continuous improvement opportunities that increase the effectiveness of the Chapter.</li><li>Implement, evolve and support consistent ways of working across the Chapter and CBA business that align to industry standards.</li><li>Uplift Chapters maturity by fostering a culture of sharing, learning and problem solving across Chapter Areas.</li><li>Facilitate the constructive resolution of conflicts which may arise both internally &amp; externally to the Chapter.</li><li>Participate and contribute to the Practice and/or Chapter including maintaining technical experience commensurate with their specific Chapter.</li><li>Providing oversight and leadership of data projects with strategic business and customer value for Business Banking Optimizing the resource model for efficiency and scale with resources located onshore and offshore.</li><li>Building world-class team culture and engagement with a strong focus on career development.</li><li>Adhere to the Code of Conduct. The Code of Conduct sets the standards of behaviour, actions and decisions we expect from our people</li></ul> Essential Skills: An experienced senior leader who has demonstrated success achieving measurable performance improvements across large and complex businesses.<ul><li>18+ years’ experience preferably gained in Banking and Finance.</li><li>Have hands-on experience working with the Ability to drive and influence senior level stakeholder engagement across business and technology.</li><li>Leadership experience across multi-disciplinary teams</li><li>Excellent communication skills, especially in relation to verbal communications and proven presentation skills to large audience.</li><li>Experienced technologist that understands data platforms and their capabilities</li></ul>Technical Skills <ul><li>Cloud: AWS, Serverless, Containers, and VM Hosting </li><li>Databases: AWS Database technologies (Aurora, RDS, Redis), ElastiCache, Oracle </li><li>Languages: Typescript, Java (Must have), Python (Desirable), C# </li><li>Eventing: SQS, SNS, EventBridge, KAFKA (MKS) </li><li>Engineering: Github, Github Actions, Terraform Enterprise, Artifactory, AKKA, SST </li><li>Observability: OpenTelemetry, Prometheus, Grafana, Observe, CloudWatch </li></ul>Design skills <ul><li>Testing: TDD, BDD, Automation Framework </li><li>System Design: Tech debt, data-intensive applications, database design, API design, microservices, event-driven and serverless architecture </li><li>Engineering: Deployment methodologies, SRE </li><li>Payments: NPP, SWIFT, BIAN </li><li>AI: AI in engineering (e.g., Cline, CoPilot), RAG, MCP, Gen-AI, Agentic-AI, machine learning </li></ul>Certifications (preferrable) <ul><li>AWS: AWS Solutions Architect and DevOps Engineer Professional </li><li>AI: AWS AI Practitioner and Machine Learning Specialty </li><li>Containers: Certified Kubernetes Administrator (CKA) / Certified Kubernetes Developer (CKD)</li><li>Your Qualifications</li><li>Security: Vault, Security Management, Parameter Store, AWS Certificate Manager, AWS Secrets Manager </li></ul>Education Qualifications: Bachelors or Master's degree in engineering in Computer Science/Information Technology.If you're already part of the Commonwealth Bank Group (including Bankwest, x15ventures), you'll need to apply through <a href="https://sidekick.hr.cba" rel="noopener noreferrer" target="_blank">Sidekick</a> to submit a valid application. We’re keen to support you with the next step in your career.We're aware of some accessibility issues on this site, particularly for screen reader users. We want to make finding your dream job as easy as possible, so if you require additional support please contact HR Direct on 1800 989 696.Advertising End Date: 19/09/2025<h4>Experience Level</h4>Executive Level

Commonwealth Bank of Australia

Chief Engineer

IVI BSP Display-Touch-Audio Subsystem Engineer<h4>At Visteon, the work we do is both relevant and recognized—not just by our organization, but by our peers, by industry-leading brands, and by millions of drivers around the world. That’s YOUR work.</h4><h4>And, as a truly global technology leader in the mobility space, focused on building cross-functional AND cross-cultural teams, we connect you with people who help you grow.</h4><h4>So here, whatever we do is not a job. It’s a mission. As a multi-billion-dollar leader of disruptive change in the industry, we are shaping the future, while enabling a cleaner environment. No other industry offers more fast-paced change and opportunity. We are in the midst of a mobility revolution that will completely change the way we interact with our vehicles, reduce the number of car accidents and fatalities, and make the world a cleaner place. </h4><h4>Visteon is at the epicenter of this mobility revolution.</h4><h4>Two major trends in the automotive industry – the shift to electric vehicles and vehicles with autonomous safety technologies – have created unique opportunities for Visteon. We are the only automotive provider focused exclusively on cockpit electronics – the fastest-growing segment in the industry.</h4><h4>Detailed description: The mission of this role is to design, develop, test and debug BSP software components to build Display-Touch-Audio Subsystem capabilities in In-Vehicle infotainment systems. How You Will Spend Your Days • Review requirement specifications and work along with requirements team to resolve issues in the specification and eventually signoff the specification. • HSIS review and correction along with hardware team. • Board bring up activities for Display, Touch, Audio subsystem (Serializer-Deserializer, Platform specific frameworks, GMSL/LVDS / FPD Link, DSI/DP, Touch Firmware, Audio calibration and TDM /PCM/DSP) in Linux, Android and QNX systems. • Interact with hardware teams for board bring up activities, calibration &amp; certification activities and to root cause hardware level issues. • Interact with cross-functional teams within Visteon and as well as with external teams like chipset vendors to resolve dependencies during development and fixing issues. • Perform root cause analysis for the issues observed and resolve issues during development, stability and maintenance phase of the project. • Create documentations for high level design, detailed design and test plans for the software modules. • Develop and integrate tools/scripts to automate testing. • Run development testing and document the test reports. • Create efficient reports with respect to software development, issues resolution and testing. Technical Knowledge and Skills • Bachelor’s degree in engineering or related field in Computer Science or Electronics. • At least 10 to 12 years of experience in developing BSP software components in Linux and Android platforms. o Good Knowledge of Linux &amp; QNX device drivers as well as peripheral subsystems. o Strong in C programming skills. o Working experience in Android AOSP/Linux based infotainment and build environments o Development experience in Display, Touch, Audio subsystem drivers (Serializer-Deserializer, Platform specific frameworks, GMSL/LVDS FPD Link, DSI, Touch Firmware, Audio calibration and TDM /PCM/DSP configurations, I2S, A2B). o Experience on DSI, DP port configurations across various SoC platforms like Qualcomm, Samsung, MediaTek. o Display bridge chip bring-up/configuration experience. o DRM, Surface flinger, Openwfd, screen related understanding to debug issues. o TFT panel display timing configuration and debugging. o Touch controller firmware update, Driver configuration parsing mechanisms. o Audio driver usage in different chip vendor’s platform; understanding of audio routing; configurations in terms of OS, SoC platform. o Development experience in serial protocols like I2C, SPI and UART. o Working experience in QNX hypervisor-based systems o Good knowledge and working experience on Qualcomm, MediaTek and Samsung SoC platforms. o Proficient in handling hardware debugging tools like oscilloscope, saleae analyzer, EVK platforms, JTAG debugger • Creative &amp; strong problem-solving capability resulting in good solution to technical complex software defects • Strong communication and inter-personal skills</h4><h4>More Good Reasons to Work for Visteon Focusing on the Future</h4><h4>Our company strategy focuses on leading the evolution of automotive digital cockpits and safety solutions. This strategy is driven by constant innovation, and you will support our efforts through your role. We are recognized across the industry for innovation. We have a strong book of business that is expected to drive future growth, along with a customer base that includes almost every automotive manufacturer in the world.</h4><h4>Company Culture</h4><h4>Working at Visteon is a journey in which our employees can develop their strengths and advance their careers while making a difference globally. Join us and help change the world and how we interact with our vehicles. Visteon is where the best technical talent creates the future. Learn more about our culture <a href="https://www.visteon.com/careers/company-culture/" rel="noopener" target="_blank">here.</a></h4><h4> </h4><h4>About Visteon</h4><h4> </h4><h4>Visteon is a global technology company serving the mobility industry, dedicated to creating a more enjoyable, connected and safe driving experience. The company’s platforms leverage proven, scalable hardware and software solutions that enable the digital, electric, and autonomous evolution of our global automotive customers. Visteon products align with key industry trends and include digital instrument clusters, displays, Android-based infotainment systems, domain controllers, advanced driver assistance systems and battery management systems. The company is headquartered in Van Buren Township, Michigan, and has approximately 10,000 employees at more than 40 facilities in 18 countries. Visteon reported sales of approximately $2.8 billion and booked $5.1 billion of new business in 2021.Learn more at <a href="http://www.visteon.com/" rel="noopener" target="_blank">www.visteon.com</a>.</h4><h4>Follow Us</h4><h4>For more information about our company, technologies and products, follow us on <a href="https://www.linkedin.com/company/visteon" rel="noopener" target="_blank">LinkedIn, </a><a href="https://twitter.com/Visteon" rel="noopener" target="_blank">Twitter,</a> <a href="https://www.facebook.com/VisteonCorporation" rel="noopener" target="_blank">Facebook, </a><a href="https://www.youtube.com/user/Visteon" rel="noopener" target="_blank">YouTube </a>and <a href="https://www.slideshare.net/VisteonCorporation" rel="noopener" target="_blank">Instagram. </a>You can also follow our careers-focused channels on <a href="https://twitter.com/VisteonCareers" rel="noopener" target="_blank">Twitter </a>and <a href="https://www.facebook.com/VisteonCareers" rel="noopener" target="_blank">Facebook </a>to keep up with our latest job postings and the great work our employees are doing.</h4><h4>Experience Level</h4>Senior Level

Visteon

SoC Senior Design and Integration Engineer, Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.</li><li>5 years of experience in ASIC/SoC development with Verilog/SystemVerilog.</li><li>Experience in one or more SoC Integration domains and flows (Clocking or debug or fabrics/NoC or Security or low power methodologies).</li><li>Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT). </li></ul> <h4>Preferred qualifications:</h4><ul><li>Experience with programming languages (e.g., Python, C/C++ or Perl).</li><li>Experience in SoC designs and integration flows.</li><li>Knowledge of bus architectures, fabrics/NoC or memory hierarchies.</li><li>Knowledge of high performance and low power design techniques.</li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.<h4>Responsibilities</h4><ul><li>Own microarchitecture, implementation and Integration of SoC Chassis and subsystems.</li><li>Perform Quality check flows like Lint, CDC, RDC, VCLP.</li><li>Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Identify and drive Power, Performance and Area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Senior Level

Google India Pvt Ltd

Embedded Systems Engineer

BIM Manager Arcadis is the world's leading company delivering sustainable design, engineering, and consultancy solutions for natural and built assets.We are more than 36,000 people, in over 70 countries, dedicated to improving quality of life. Everyone has an important role to play. With the power of many curious minds, together we can solve the world’s most complex challenges and deliver more impact together.Role description:BIM Manager – ANA Mobility - Plan and execute project related outputs for Design &amp; Build and State DoT projects with proficiency in various Bentley tools as mentioned in Mandatory Technical Skills. Will have to be compliant with Arcadis 100% BIM requirements and industry practices, 3D Modelling, CAD production. Should have handled tasks independently with accountability and had demonstrated good communication and coordination skills with GEC teams and ANA teams Specific US experience is most desirable.Role accountabilities:<ul><li>Responsible for end-to-end project delivery for Roadway and Bridge related tasks.</li><li>Preparation / Finalization of various roadway related drawings at various stages of projects.</li><li>Preparation of project progress and status reports</li><li>Ability to be able to work and manage the team, guide, and mentor them</li><li>Should have worked for US Projects and must be conversant with AASHTO and various DOT specifications and standards.</li></ul> Mandatory Technical Skills:<ul><li>Compliant with Arcadis 100% BIM requirements and industry practices, 3D Modelling, CAD production</li><li>Able to create, review and manage federated model from multi-disciplinary models</li><li>Ability to delegate and review the tasks from Junior BIM Modelers</li><li>Ability to create, manage and execute BIM Execution Plan</li><li>Should have expertise in MicroStation, ORD, and other Bentley BIM complaint tools</li><li>Good understanding and Knowledge on international codes like AASHTO, along with various other International Codal Practices and Standards, CAD Standards for more than one DOT in USA.</li><li>Project Experience using various DOT (Department of Transportation) standards.</li><li>Experience in MS Office software including Word, Excel and PowerPoint.</li><li>Able to communicate and work with the NA team including junior and senior engineers</li><li>Responsibility to work to required standards and quality assurance procedures</li><li>Understand and put into practice health and safety requirements</li><li>Full understanding of US units of measure.</li><li>Read, write, and speak -English.</li></ul>Additional Skills:<ul><li>Good Experience in managing the tasks in International Projects –United States (desirable), Middle East, UK and any other developed countries.</li><li>Software: Bentley Concept Station, Micro Station – (FDOT, GDOT), FDOT CAD Standard Tools, GDOT Design Standard tools</li></ul>Qualifications &amp; Experience:<ul><li>B.E / BTech in Civil Engineering</li><li>Minimum 15 years of experience in Design Consulting Environment as of March 31, 2025.</li><li>Minimum of 6 years of working experience for International Design Projects for Highway / Roadway Design and minimum of 4 years of working experience for USA projects in delivering on various multiple project deliverable with BIM compliance. Having work experience on Design &amp; Build Projects is added advantage. Currently should be at Arcadis Level 7 (2 years period at Level 7 as of March 31, 2022, is desirable) and designated as “Principal BIM Modeler” in appropriate discipline can apply.</li><li>Overall requirements, roles and responsibilities will be as per GEC India Career Framework document.</li></ul>Why Arcadis?We can only achieve our goals when everyone is empowered to be their best. We believe everyone's contribution matters. It’s why we are pioneering a skills-based approach, where you can harness your unique experience and expertise to carve your career path and maximize the impact we can make together.You’ll do meaningful work, and no matter what role, you’ll be helping to deliver sustainable solutions for a more prosperous planet. Make your mark, on your career, your colleagues, your clients, your life and the world around you.Together, we can create a lasting legacy.Join Arcadis. Create a Legacy.Our Commitment to Equality, Diversity, Inclusion &amp; BelongingWe want you to be able to bring your best self to work every day which is why equality and inclusion is at the forefront of all our activities. Our ambition is to be an employer of choice and provide a great place to work for all our people. We are an equal opportunity employer; women, minorities, and people with disabilities are strongly encouraged to apply. We are dedicated to a policy of non-discrimination in employment on any basis including race, caste, creed, colour, religion, sex, age, disability, marital status, sexual orientation, and gender identity. <h4>Experience Level</h4>Mid Level

Arcadis India Pvt Ltd

Senior Architect

Silicon Micro-architecture and RTL Lead , Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.</li><li>10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).</li><li>Experience in micro-architecture and design IPs and Subsystems.</li><li>Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).</li></ul> <h4>Preferred qualifications:</h4><ul><li>Experience with scripting languages (e.g., Python or Perl).</li><li>Experience in SoC designs and integration flows.</li><li>Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies..</li><li>Knowledge of high performance and low power design techniques.</li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.<h4>Responsibilities</h4><ul><li>Drive development of Complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization.</li><li>Own micro-architecture and implementation of IPs and subsystems.</li><li>Work with Architecture, Firmware and Software teams to drive feature closure and develop micro-architecture specifications.</li><li>Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Identify and drive Power, Performance and Area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Senior Level

Silicon RTL Design Engineer Networking, Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.</li><li>4 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.</li><li>Experience in micro-architecture and design of IPs and Subsystems.</li><li>Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).</li></ul> <h4>Preferred qualifications:</h4><ul><li>Experience in Networking domain like Packet processing, bandwidth management, congestion control etc.</li><li>Experience with scripting languages (e.g., Python or Perl).</li><li>Knowledge of bus architectures, fabrics/NoC, processor design, or memory hierarchies.</li><li>Knowledge of high performance and low power design techniques. </li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.In this role, you will develop to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.<h4>Responsibilities</h4><ul><li>Own microarchitecture and implementation of IPs and subsystems in the Networking domain.</li><li>Work with design team members to close feature definitions and develop microarchitecture specifications. </li><li>Participate in design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Work on Power, Performance and Area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Mid Level

Senior Engineer - Network modeling (Infowork ICM)<h4>Company Description</h4>Work with Us. Change the World.At AECOM, we're delivering a better world. Whether improving your commute, keeping the lights on, providing access to clean water, or transforming skylines, our work helps people and communities thrive. We are the world's trusted infrastructure consulting firm, partnering with clients to solve the world’s most complex challenges and build legacies for future generations.There has never been a better time to be at AECOM. With accelerating infrastructure investment worldwide, our services are in great demand. We invite you to bring your bold ideas and big dreams and become part of a global team of over 50,000 planners, designers, engineers, scientists, digital innovators, program and construction managers and other professionals delivering projects that create a positive and tangible impact around the world.We're one global team driven by our common purpose to deliver a better world. Join us.<h4>Job Description</h4><ul><li>Contribute to engineering design assignments in a team environment on large-scale project teams.</li><li>Candidate should have minimum 5 years working experience on wastewater modelling for ANZ and UK &amp; I region especially on model calibration &amp; verification.</li><li>Candidate should be well versed with Infoworks ICM hydraulic modelling software.</li><li>Having hands on experience with modeling tools like Water GEMS, SewerGEMS, StormCAD, PCSWMM, HEC-RAS, GeoPak would be advantage.</li><li>Capable for leading the project, coordinating with Lead Office, mentoring juniors and ensuring quality checks.</li><li>Complete design activities to specified standards including earthworks modelling and design, sanitary and storm sewer design, watermain design, grading of roads and drive isles, lot grading, and stormwater management design of ponds and other retention systems.</li></ul><h4>Qualifications</h4><ul><li>Master of Engineering degree (or equivalent education) in an appropriate engineering discipline from an accredited college or university. </li><li>Chartered Engineer (CEng), or Professional Engineer (PE) license or equivalent in the relevant field from any global organization (e.g., Institution of Civil Engineers, UK).</li><li>Highly motivated, hardworking, interpersonal, and enthusiastic team player that is willing to learn and adapt to change.</li><li>US/UK/Canada Experience will be added advantage</li><li>Good communication skills, and ability to work well independently at times.</li><li>Able to see the “bigger picture” and take a birds-eye view of projects</li><li>Confident, with the ability to work either independently or as part of a team.</li><li>Ability to work to deadlines and under pressure.</li><li>Accountability for assigned work.</li><li>Accuracy &amp; precision of work.</li><li>Willingness to learn and develop.</li><li>Excellent written and verbal communication skills</li><li>Strong problem-solving skills</li><li>Enthusiastic and Self-motivated.</li><li>Work well within a multidisciplinary team</li></ul><h4>Additional Information</h4>AECOM provides a wide array of compensation and benefits programs to meet the diverse needs of our employees and their families. We also provide a robust global well-being program. We’re the world’s trusted global infrastructure firm, and we’re in this together – your growth and success are ours too. As an Equal Opportunity Employer, we believe in each person’s potential, and we’ll help you reach yours.#LI-FS1About AECOM AECOM is proud to offer comprehensive benefits to meet the diverse needs of our employees. Depending on your employment status, AECOM benefits may include medical, dental, vision, life, AD&amp;D, disability benefits, paid time off, leaves of absences, voluntary benefits, perks, flexible work options, well-being resources, employee assistance program, business travel insurance, service recognition awards, retirement savings plan, and employee stock purchase plan. AECOM is the global infrastructure leader, committed to delivering a better world. As a trusted professional services firm powered by deep technical abilities, we solve our clients’ complex challenges in water, environment, energy, transportation and buildings. Our teams partner with public- and private-sector clients to create innovative, sustainable and resilient solutions throughout the project lifecycle – from advisory, planning, design and engineering to program and construction management. AECOM is a Fortune 500 firm that had revenue of $16.1 billion in fiscal year 2024. Learn more at aecom.com. What makes AECOM a great place to work You will be part of a global team that champions your growth and career ambitions. Work on groundbreaking projects - both in your local community and on a global scale - that are transforming our industry and shaping the future. With cutting-edge technology and a network of experts, you’ll have the resources to make a real impact. Our award-winning training and development programs are designed to expand your technical expertise and leadership skills, helping you build the career you’ve always envisioned. Here, you’ll find a welcoming workplace built on respect, collaboration and community - where you have the freedom to grow in a world of opportunity. As an Equal Opportunity Employer, we believe in your potential and are here to help you achieve it. All your information will be kept confidential according to EEO guidelines. <h4>Experience Level</h4>Senior Level

Aecom India Pvt Ltd

Senior Network Engineer

Silicon Senior Physical Design Engineer, TPU, Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor’s degree in Electrical Engineering or equivalent practical experience.</li><li>5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.</li><li>Experience with System on a Chip (SoC) cycles.</li><li>Experience in high-performance, high-frequency, and low-power designs.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Master’s degree in Electrical Engineering.</li><li>Experience in coding with System Verilog and scripting with TCL.</li><li>Experience with VLSI design in SoC or multiple-cycles of SoC in ASIC design.</li><li>Experience with layout verification and design rules.</li></ul><h4>About the job</h4>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.<h4>Responsibilities</h4><ul><li>Define and drive the implementation of physical design methodologies.</li><li>Take ownership of one or more physical design partitions or top level.</li><li>Manage timing and power consumption of the design.</li><li>Contribute to design methodology, libraries, and code review. 
</li><li>Define the physical design related rule sets for the functional design engineers.</li></ul><h4>Experience Level</h4>Senior Level

Design Engineer

BIM Manager We’re seeking talented minds&nbsp;who thrive on clarity, collaboration, and long-term impact. Step into work that matters. • Experience - 10+ years What You'll Gain• Projects at grand scale.• Guidance that sharpens your craft.• A culture that balances creativity with growth. Send your updated CV &amp; portfolio&nbsp;now.

Edifice Consultants

Verification Engineer<h1> </h1>Experience:&nbsp;4-10 YearsJob Descriptions &amp; RequirementsYou should have prior knowledge and experience with UVM verification and UVM environment development Additional responsibilities include:• Help develop test plan definition and development• Micro-architecture design verification, RTL verification, and documentation• Top-level and block-level performance verification, power, and use-case verification; and• Support test program development, chip validation, and chip life until production maturity.• Team Management and Building• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development. Qualifications :• Experience in UVM verification and UVM environment development (must have)• Proficient in test plan definition and testcase development in C/Assembly/System Verilog Expertise

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