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Software Engineer IIAt Medtronic you can begin a life-long career of exploration and innovation, while helping champion healthcare access and equity for all. You’ll lead with purpose, breaking down barriers to innovation in a more connected, compassionate world.<h4>A Day in the Life</h4>As a Controls Software Engineer working at Medtronic, you will be a significant contributor in the development of control algorithms that supports, legacy, current and future generations of robotic surgical instruments. You will create software solutions that run on a sophisticated real-time embedded platform, using embedded sensor and actuator hardware to deliver high-bandwidth, precise and robust instrument response. In addition, this role will involve engagement with the electromechanical design of surgical instruments at all stages – with a focus on control software requirements development that is compatible with the test, verification, and validation of a safety-critical system.Responsibilities may include the following and other duties may be assigned:<ul><li>Design and develop software in Matlab - Simulink and Stateflow that enables surgeons and operating-room staff to control “Hugo”; a Robotic Assisted Surgery System.</li><li>Integrate and test new controller software on hardware and with the rest of the robotic platform.</li><li>Contribute to the development of model based control system for Hugo.</li><li>Partner with the greater software organization, systems engineering, and validation groups.</li><li>Define and review software requirements.</li><li>Conduct hardware-in-loop testing of prototype as well as product software.</li><li>Act as an independent reviewer of Simulink models to ensure that all software meets quality standards.</li><li>Prepare and participate in design reviews.</li><li>Document or participate in the documentation of the software including architecture and design detail, unit testing, anomaly tracking and reports.</li></ul>Required knowledge and experience:<ul><li>Bachelor’s Degree with 4 to 8 years of relevant experience, or advanced degree with 4+ years of relevant experience.</li><li>Experience developing software to control complex dynamical systems, preferably in regulated industries.</li><li>Experience in analysis of complex dynamical systems (mechatronics preferred).</li><li>Proficient use of Matlab - Simulink and Stateflow to design and develop complex software products.</li><li>Experience in Embedded C/C++ software development.</li><li>Experience with real-time operating systems (QNX/VxWorks or equivalent).</li><li>Design and implementation of safety critical software – this includes aspects of risk analyses, Failure Modes and Effects Analysis, Redundancy , Coding Standards and Verification of software implementations.</li><li>Strong understanding of the fundamentals in signal processing, especially in the context of discrete systems.</li><li>Knowledge of software development processes such as the V-model, requirement engineering, impact analysis.</li><li>Good communication and stakeholder management skills. Nice to Have</li><li>Experience developing software in a Linux environment.</li><li>Familiarity with virtual machines, networking concepts.</li><li>Experience with common software development tools, including build automation, code coverage, unit testing, static analysis, debugging, and source control (git preferred).</li><li>Familiarity with Simulink Coder and an in-depth understanding of code generation.</li><li>Knowledge of mathematics for controlling robotic systems, including multi-body kinematics, feedback controllers, and signal processing.</li><li>Experience with medical product development is highly desired, including regulatory processes, safety considerations, and hands-on experience with medical devices and surgical instruments.</li><li>Strong interpersonal skills and attention to detail, with ability to work collaboratively with cross-functional teams to build consensus and establish common goals.</li><li>Experience with diverse, cross functional teams; Geodiversity spanning an international environment is a bonus.</li><li>Experience in model-based product software development for real-time applications.</li><li>Unit and integration testing of software.</li><li>Software testing with plant models.</li><li>Software architecture design and documentation.</li></ul>Physical Job Requirements The above statements are intended to describe the general nature and level of work being performed by employees assigned to this position, but they are not an exhaustive list of all the required responsibilities and skills of this position. <h4>Benefits &amp; Compensation</h4>Medtronic offers a competitive Salary and flexible Benefits Package A commitment to our employees lives at the core of our values. We recognize their contributions. They share in the success they help to create.  We offer a wide range of benefits, resources, and competitive compensation plans designed to support you at every career and life stage. <h4>About Medtronic</h4>We lead global healthcare technology and boldly attack the most challenging health problems facing humanity by searching out and finding solutions. Our Mission — to alleviate pain, restore health, and extend life — unites a global team of 95,000+ passionate people.  We are engineers at heart— putting ambitious ideas to work to generate real solutions for real people. From the R&amp;D lab, to the factory floor, to the conference room, every one of us experiments, creates, builds, improves and solves. We have the talent, diverse perspectives, and guts to engineer the extraordinary.Learn more about our business, mission, and our commitment to diversity <a href="http://www.medtronic.com" rel="noopener noreferrer" target="_blank">here</a>   <h4>Experience Level</h4>Mid Level

India Medtronic Pvt. Ltd

Software Engineer 1

Autosar-Architect The architect will be responsible in formulating the product roadmap for customer projects, work with Product Owners and Business Leaders to define the technical product strategy. The individual will also participate in customer meetings to proactively pitch technical solution from KPIT AUTOSAR practice and can grow to becoming a Product owner or Senior Program Manager.Roles and Responsibility:<ul><li>Do Technical RCA of Problems and Systemic Improvements</li><li>Create Software Architecture and review Project Level Technical workflows</li><li>Do Project Level Technical Impact Analysis of Changes</li><li>Assess and Improve Team Training and Competency</li><li>Review design and performance optimization</li><li>Review estimates of tasks and functions in projects</li><li>Review Technical approach, estimation, technical risks and solution of proposals</li><li>Convert customer requirements to software requirements</li><li>Automate and implement tool chain for quality and productivity improvement</li></ul>&nbsp;RequirementESSENTIAL SKILLS /COMPETENCIES<ul><li>Hands on Experience in Embedded C coding and assembly language</li><li>Strong debugging and analytics skills using tools like CANoe/CANalyzer/CANstress</li><li>Experience in AUTOSAR based Software Development</li><li>Working experience in any of following areas</li><li>Hands on experience in AUTOSAR Integration and configuration of BSW modules like OS/RTE/CAN/COM/NVM</li><li>Experience in any one protocol development like CAN / UDS / Ethernet / J1939</li><li>Experience in Fault Handler/DEM/EOL/EDR modules development</li><li>Hands on experience in bootloader Integration</li></ul> PREFFERED SKILLS /COMPETENCIES<ul><li>Strong oral and written communication skills</li><li>Strong Knowledge on Microcontroller</li><li>Strong Knowledge on Embedded systems</li><li>Good Knowledge on ASPICE/ISO26262/MISRA Guidelines</li><li>Experience in configuration management/change management methodologies</li></ul> EXPERIENCE<ul><li>8-12 Years</li></ul>

Kpit Technologies Limited

Architect

Bluetooth Testing Engineer Responsibilities:Test Planning and Design:• Develop comprehensive test plans and strategies for Bluetooth and co-existence testing.• Design test cases to assess Bluetooth device performance in the presence of other wireless technologies (e.g., Wi-Fi, LTE, Zigbee).• Identify potential interference sources and scenarios for coexistence testing. Test Execution:• Set up and configure test environments, including hardware and software components.• Execute test cases and record detailed results.• Utilize test equipment such as spectrum analyzers, network analyzers, and Bluetooth protocol analyzers.• Perform automated and manual testing to assess coexistence performance. Analysis and Reporting:• Analyze test results to identify issues related to coexistence and interference.• Collaborate with cross-functional teams to diagnose and resolve coexistence issues.• Document test procedures, results, and findings in detailed reports.• Provide recommendations for improving Bluetooth coexistence performance. Requirements•Bachelor’s or master’s degree in computer science, Electrical Engineering, or a related field.•3 to 6 years of experience in BT Testing or embedded systems.•Strong problem-solving and analytical skills.

Eximietas Design

Test Engineer

Verification EngineerThe Verification Engineer will be responsible for ensuring the quality and reliability of hardware and network systems. They will work closely with the engineering team to develop and execute verification plans, analyze test results, and identify and resolve any issues. The role requires strong problem-solving skills, attention to detail, and the ability to work effectively in a team environment.

eInfochips ( An Arrow Company )

Testing Engineer

Windchill Architect We are looking for skilled professionals in PTC Windchill for below role: Job Role:&nbsp;Windchill ArchitectExperience: 10 -14 yearsLocation: Hyderabad Immediate joiners are preferred. Interested candidates, please send your resume.

Birlasoft Limited

Storage Firmware Developer Key Responsibilities<ul><li>Develop and maintain firmware for storage devices.</li><li>Implement new features and optimize existing functionalities.</li><li>Perform debugging and troubleshooting of firmware issues.</li><li>Collaborate with cross-functional teams to ensure seamless integration of firmware with hardware.</li><li>Create and maintain documentation for firmware development processes.</li></ul> Requirements<ul><li>Bachelor’s or master’s degree in computer science, Electrical Engineering, or a related field.</li><li>2 to 10+ years of experience in firmware development for storage or embedded systems.</li><li>Strong firmware design and debug experience using assembly and C programming.</li><li>Deliver on cutting-edge storage products with interfaces like SAS, SATA, NVMe, PCIe.</li><li>Work with cross functional teams to develop HDD/SSD/NAND products would be a strong plus.</li><li>Strong problem-solving and analytical skills.</li></ul>

Embedded Software Developer

Design for Test Engineer Job DescriptionWe are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with a minimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities<ul><li>Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans.</li><li>Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy.</li><li>Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&amp;R IP blocks for Scan, MBIST and other test interfaces.</li><li>Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing.</li><li>Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet.</li><li>Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs.</li><li>Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations.</li><li>Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types.</li><li>Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues.</li><li>Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs.</li><li>Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting.</li><li>Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow.</li><li>Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory.</li><li>Knowledge of LogicBIST with Test point insertion, X-blocking.</li><li>Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements.</li><li>Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug.</li><li>Ability to perform volume diagnostics on the parts to isolate and improve the patterns.</li></ul> Requirements<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design for Test.</li><li>Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows.</li><li>Prior experience working on IP level and SOC level DFT projects.</li><li>Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc.</li><li>Worked in full chip design or complex IP delivery in the area of DFT.</li><li>Experience in post silicon debug, diagnosis and yield enhancements is a plus.</li></ul>

Senior Test Engineer

Consultant - Fatigue & Damage Tolerance Engineer Capgemini is hiring below position:- Designation: ConsultantExperience: 4–6 Years Job Skill: Fatigue &amp; Damage Tolerance EngineerLocation: Bengaluru Note: Please mention the Designation while sharing your CV for reference.To apply, please email your CV.

Capgemini

Fabrication Quality Engineer

Design Verification Engineer This job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job OverviewWe are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description<ul><li>Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.</li><li>Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM</li><li>Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.</li><li>Analyze and implement System Verilog assertions and coverage (code, toggle, functional).</li><li>Provide mentorship and technical guidance to junior verification engineers.</li><li>Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.</li><li>Ensure verification signoff criteria are met and documentation is comprehensive.</li><li>Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.</li><li>Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.</li><li>Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.</li></ul> Qualifications<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>Master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design Verification.</li><li>Expertise in UVM (Universal Verification Methodology) and System Verilog.</li><li>Prior experience working on IP level and SOC level verification projects.</li><li>Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).</li><li>Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.</li><li>Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.</li><li>Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Proficiency in scripting languages such as shell, Makefile, and Perl.</li><li>Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.</li><li>C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.</li></ul>

Assistant Design Engineer

RTL ENGINEER Experience: 4+ YearsThis job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job Description Required<ul><li>Solid RTL coding experience including</li><li>Microarchitecture of design</li><li>System Verilog and Verilog coding using provided coding styles.</li><li>Understanding of SDC</li><li>Understanding STA reports and how to adjust RTL accordingly.</li><li>Designing for error cases and debug of IP</li><li>Understanding of CDC logic</li><li>Knowledge of lint rules and exceptions</li><li>Design and use of block level simulations to bring up IP.</li><li>Knowledge of AMBA buses and when to use them.</li></ul> Job Description Preferred<ul><li>Experience&nbsp;leading small design team.</li><li>C coding / Firmware skills</li><li>Knowledge on common processor architectures&nbsp;(ARM, RiscV)</li><li>FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA.</li><li>Lab brings up experience, scripting.</li><li>Relevant tool experience such as: Socrates, Core Consultant in addition&nbsp;to standard simulation tools (xcellium, vcs, etc)</li><li>Emulation experience&nbsp;(Zebu, Palladium, etc)</li><li>Board knowledge, component selection, probing, debug.</li><li>JTAG debugging experience (Coresight, Lauterbach, etc).</li><li>Low power design techniques</li></ul> Qualifications<ul><li>E./B.Tech. degree at minimum.</li></ul>

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Junior Network Engineer

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