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Scada - Ignition Engineer We're hiring below position: Position: Scada - Ignition Engineer&nbsp;Experience: 4 to 6 years If you're interested, please share your profile.

Capgemini

Electrical / Electronics Engineer

Middleware/QNX-Architect The architect will be responsible in formulating the product roadmap for customer projects, work with Product Owners and Business Leaders to define the technical product strategy. The individual will also participate in customer meetings to proactively pitch technical solution from KPIT Adaptive AUTOSAR practice and can grow to becoming a Product owner or Senior Program Manager. Roles &amp; Responsibilites:<ul><li>Do Technical RCA of Problems and Systemic Improvements</li><li>Create Software Architecture and review Project Level Technical workflows</li><li>Do Project Level Technical Impact Analysis of Changes</li><li>Assess and Improve Team Training and Competency</li><li>Review design and performance optimization</li><li>Review estimates of tasks and functions in projects</li><li>Review Technical approach, estimation, technical risks and solution of proposals</li><li>Convert customer requirements to software requirements</li><li>Automate and implement tool chain for quality and productivity improvement</li></ul> RequirementESSENTIAL SKILLS /COMPETENCIES<ul><li>Hands on experience Embedded C / C++ 11/14/17</li><li>Hands on debugging skills using Vector tools like</li><li>Working experience Yocto Linux/QNX or GHS Operating Systems and Hypervisor</li><li>Ethernet/Internet Protocols (TCP/UDP/IP/REST/HTTP etc)/SOME/IP/Service Oriented Architecture</li><li>Linux driver layer and Linux internal architecture</li><li>Good oral and written communication skills</li><li>Basic Knowledge on Microcontroller basics</li></ul> PREFFERED SKILLS /COMPETENCIES<ul><li>Understanding of Adaptive AUTOSAR specifications</li><li>Knowledge in Object Oriented Programming (Design patterns/threading/lambda expressions)</li><li>Understanding UML modeling</li><li>Good Knowledge on ASPICE/ISO26262/MISRA Guidelines</li><li>Experience in configuration management/change management methodologies</li></ul> EXPERIENCE<ul><li>8-12 Years</li></ul>

Kpit Technologies Limited

DevOps Architect

Principal Memory Design Engineer<h4>
 
 General Information
 </h4>






 Job Title
 

 Principal Memory Design Engineer
 



 Job ID
 

 12388
 



 Country
 

 India
 



 City
 

 Hyderabad
 



 Date Posted
 

 28-Jul-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 R&amp;D Engineering
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

<h4 id="isPasted">Alternate Job Titles:</h4><ul><li>Principal Memory Design Engineer</li></ul><h4> </h4><h4>We Are:</h4>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.<h4>You Are:</h4>You are an accomplished and innovative engineer passionate about pushing the boundaries of embedded memory design. With a strong foundation in electrical and electronics engineering, you thrive in dynamic environments where complex problem-solving and creativity are at the forefront. Your expertise in deep submicron and FinFET technology, coupled with hands-on experience in SRAM, register file, TCAM, and ROM architectures, positions you as a technical leader who can address intricate design challenges. You excel in both independent and collaborative settings, proactively seeking solutions and driving projects to timely completion. Your ability to communicate effectively with diverse teams, mentor junior engineers, and network with senior personnel ensures you can influence and inspire across the organization. With a keen eye for detail and a holistic understanding of the full embedded memory design flow, you are committed to delivering state-of-the-art solutions that set industry benchmarks. Your adaptability, customer focus, and continuous learning mindset make you a valued contributor to Synopsys’ mission of technological excellence.<h4> </h4><h4>What You’ll Be Doing:</h4><ul><li>Develop advanced SRAM, register file, TCAM, and ROM architectures and implement innovative circuit techniques for embedded memory IP.</li><li>Lead schematic entry, simulation of major blocks, layout planning, and supervise layout activities, collaborating closely with the CAD team for full verification and model generation.</li><li>Design and implement low-power, area-efficient embedded memory circuits and architectures, optimizing for performance, power, and area in leading-edge technology nodes.</li><li>Apply and expand your skills in transistor-level circuit design, memory compilers, and automation scripting to streamline design flows.</li><li>Resolve a wide range of technical issues creatively, collaborating with cross-functional teams and interfacing with both internal and external stakeholders.</li><li>Coordinate, facilitate, and monitor daily activities of project teams, ensuring alignment with project goals and timely delivery of milestones.</li><li>Engage in inter-team interactions and maintain a customer-centric approach, frequently networking with senior professionals to share expertise and insights.  </li><li>Proactively prioritize and manage multiple tasks with minimal supervision, driving projects from conception to successful completion.</li></ul><h4> </h4><h4>The Impact You Will Have:</h4><ul><li>Drive innovation in embedded memory IP, enabling the design of high-performance, energy-efficient integrated circuits for a global customer base.</li><li>Set new standards in memory design through creative problem-solving and adoption of advanced technology nodes, including FinFET.</li><li>Mentor and empower team members, fostering a collaborative and high-performing engineering culture.</li><li>Enhance Synopsys’ reputation and market leadership by delivering reliable, silicon-proven IP solutions that exceed customer expectations.</li><li>Influence project direction and contribute to strategic decisions by leveraging deep technical knowledge and industry insights</li><li>Facilitate successful project execution by identifying risks, proposing effective solutions, and ensuring timely delivery of high-quality results.</li></ul><h4> </h4><h4>What You’ll Need:</h4><ul><li>8+ years of hands-on experience across the full embedded memory design flow: architecture, circuit design, physical implementation, compiler automation, characterization, timing, and model generation.</li><li>BE/B.Tech/ME/M.Tech/MS in Electrical &amp; Electronics Engineering from a premier institute/university.</li><li>Deep understanding of SRAM/register file architectures and advanced custom circuit implementations, with direct experience in FinFET and other advanced technology nodes.</li><li>Expertise in scripting languages such as Perl and Python for design automation and flow optimization.</li><li>Strong grasp of RC circuits (1st and 2nd order), digital design fundamentals (Boolean functions, gates, multiplexers), and transfer function analysis.</li><li>Proficient knowledge of CMOS fundamentals, fabrication processes, and both digital and basic analog design principles.</li></ul><h4> </h4><h4>Who You Are:</h4><ul><li>Analytical thinker with a passion for problem-solving and innovation.</li><li>Excellent communicator, capable of articulating complex technical concepts to diverse audiences.</li><li>Strong collaborator and mentor, eager to share knowledge and support team growth.  </li><li>Self-motivated and proactive, adept at managing multiple priorities with minimal supervision.</li><li>Customer-focused, adaptable, and committed to continuous learning and professional development.</li></ul><h4> </h4><h4>The Team You’ll Be A Part Of:</h4>You will join the Embedded Memory and Logic Team within Synopsys Solutions Group, a high-impact group responsible for the end-to-end development of standard and custom embedded memories. The team’s expertise spans bit cell analysis, architecture design, characterization, verification, and delivery of memory compilers as semiconductor IP. Collaborating across disciplines and sites, the team is dedicated to delivering innovative, silicon-proven solutions that power the world’s most advanced integrated circuits.<h4>Rewards and Benefits:</h4>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Synopsys India Pvt Ltd

Embedded Systems Engineer

RTL Design Engineer <ul><li>Skill: ASIC RTL Design with LINT, CDC.</li><li>Experience: 1 to 3 Years</li><li>Notice Period: Immediate to 15 days</li></ul> Share your updated resume now.

ACL Digital

Electronic Engineer

Design Verification Engineer This job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job OverviewWe are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description<ul><li>Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.</li><li>Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM</li><li>Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.</li><li>Analyze and implement System Verilog assertions and coverage (code, toggle, functional).</li><li>Provide mentorship and technical guidance to junior verification engineers.</li><li>Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.</li><li>Ensure verification signoff criteria are met and documentation is comprehensive.</li><li>Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.</li><li>Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.</li><li>Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.</li></ul> Qualifications<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>Master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design Verification.</li><li>Expertise in UVM (Universal Verification Methodology) and System Verilog.</li><li>Prior experience working on IP level and SOC level verification projects.</li><li>Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).</li><li>Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.</li><li>Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.</li><li>Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Proficiency in scripting languages such as shell, Makefile, and Perl.</li><li>Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.</li><li>C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.</li></ul>

Eximietas Design

Assistant Design Engineer

Associate Engineer Test Engineering VIIIJob Description: To design &amp; development of Test Automation framework for verification and Validation of embedded firmware and CICD pipeline configuration.He / She Will be involved in executing projects on Vertiv’s Multiple product lines like AC Power, Thermal and DC Power. He/ She will be responsible for automating &amp; executing test scripts. Being part of Global Engineering function, will be responsible to execute the assigned job and report as per the defined communication plan. Job Specifications:<ol><li>Bachelors Engineering degree in Electronics / Electrical / Computer / IT.</li><li>Minimum 2 Years’ relevant experience into software test automation in various embedded system domains.</li><li>Strong programming skills using Python, minimum 1 years’ experience in Python. Should be worked on at least 1 end to end automation project.</li><li>HIL knowledge required using Vector tools like VT System and CANoe. CAPL knowledge will be preferred.</li><li>Testing experience with communication interface &amp; protocols i.e. RS 485, Modbus, CAN Open, Ethernet and TCP/IP, I2C, SPI is required</li><li>Strong debugging, Logical &amp; Analytical skills.</li><li>Good in CICD responsibilities like designing, implementing, and maintaining continuous integration and continuous deployment pipelines.</li><li>Hands on experience on software tools like JIRA, Bugzilla, TestRail.</li><li>Good Knowledge of C / OOPs (C++/Java) language is preferred</li><li>Prior experience on manual testing is preferable preferred</li><li>Experience into Power domain is preferred</li><li>Able to self-aligned with project and organization goals</li><li>Excellent Interpersonal Skills and ability to work in team environment </li><li>Ability to communicate effectively in both written and spoken English</li></ol>Time Travel Needed:The successful candidate will embrace Vertiv’s Core Principals &amp; Behaviors to help execute our Strategic Priorities.OUR CORE PRINCIPALS: Safety, Integrity, Respect, Teamwork, Diversity &amp; Inclusion.OUR STRATEGIC PRIORITIES  Customer Focus  Operational Excellence  High-Performance Culture  Innovation  Financial StrengthOUR BEHAVIORS  Own It  Act With Urgency  Foster a Customer-First Mindset  Think Big and Execute  Lead by Example  Drive Continuous Improvement  Learn and Seek Out DevelopmentVertiv is an Equal Opportunity/Affirmative Action employer. We promote equal opportunities for all with respect to hiring, terms of employment, mobility, training, compensation, and occupational health, without discrimination as to age, race, color, religion, creed, sex, pregnancy status (including childbirth, breastfeeding, or related medical conditions), marital status, sexual orientation, gender identity / expression (including transgender status or sexual stereotypes), genetic information, citizenship status, national origin, protected veteran status, political affiliation, or disability. If you have a disability and are having difficulty accessing or using this website to apply for a position, you can request help by sending an email to help.join@vertivco.com. If you are interested in applying or learning more about this role, please visit the company’s career page located on Vertiv.com/CareersWork Authorization No calls or agencies please. Vertiv will only employ those who are legally authorized to work in the United States. This is not a position for which sponsorship will be provided. Individuals with temporary visas such as E, F-1, H-1, H-2, L, B, J, or TN or who need sponsorship for work authorization now or in the future, are not eligible for hire.<h4>Experience Level</h4>Mid Level

Vertiv Energy Pvt Ltd

Testing Engineer

Network DeveloperThe AI2NE Org strives to be global leaders in the RDMA cluster networking domain and enable seamless, accelerated High-Performance Compute (HPC), Artificial Intelligence and Machine Learning advancements. We envision a future where artificial intelligence and machine learning revolutionize industries, reshape societies, and unlock limitless possibilities. Our vision is to be a pioneering force, driving the development and design of state-of-the-art RDMA clusters tailored specifically for AI, ML, HPC workloads. We strive to be the go-to experts in RDMA cluster architecture, leveraging our deep understanding of the unique demands of AI/ML and HPC applications. By staying at the forefront of technological advancements, we aim to redefine the boundaries of what is possible, pushing the envelope of computational capabilities and unlocking unprecedented performance. Supports the design, deployment, and operations of a large-scale global Oracle Cloud Infrastructure (OCI). Primarily focused on the development and support of network fabric and systems through a combination of a deep level understanding of networking at the protocol level coupled with programming skills. As OCI is a cloud-based network with a global footprint, this support will include hundreds of thousands of network devices supporting millions of servers, connected over a mix of dedicated backbone infrastructure, CLos Network, and the Internet.<ul><li>Will primarily use existing procedures and tools to develop and safely execute network change. However, may have to develop new procedures from time to time.</li><li>Develop solutions to enable front line support teams to act on network failure conditions. </li><li>Participate in operational rotations as either primary or secondary. </li><li>Provide break-fix support for events. Serve as the escalation point for event remediation. Participate post-event root cause analysis.</li><li>Frequently develops scripts to automate routine tasks for team and business units. </li><li>Coordinate with networking automation services for the development and integration of support tooling. </li><li>Coordinate with network monitoring to gather telemetry and create alerts rules using them.</li><li>Build dashboards to represent data at various network layers and device roles that help identify network issues, anomalies. </li><li>Collaborate with network vendor technical account team and internal Quality Assurance team to drive bug resolution and assist in the qualification of new firmware and/or operating systems.        </li><li> </li><li>Qualifications:<ul><li>Bachelor’s degree in CS or related engineering field with 2+ years of Network Engineering experience or master’s with 1+ years of Network Engineering experience.</li><li>Experience working in a large ISP or cloud provider environment. Experience in RDMA Networking is a plus.</li><li>Experience working in a network operations role.</li><li>Folks with knowledge of routing protocols such as knowledge of TCP/IP, IPv4, IPv6, DNS, DHCP and SSL.</li><li>Experience with scripting or automation and data center design – Python preferred but must demonstrate expertise in scripting or compiled language.</li><li>Experience with network monitoring and telemetry solutions.</li><li>Experience with network modeling and programming – YANG, OpenConfig, NETCONF.</li><li>Ability to use professional concepts and company objectives to resolve issues in creative and effective ways.</li><li>Excellent organizational, verbal, and written communication skills.</li><li>Participate in an on-call rotation.                                                                                                                                                                                                                                                        </li></ul></li></ul>Career Level - IC2As a world leader in cloud solutions, Oracle uses tomorrow’s technology to tackle today’s challenges. We’ve partnered with industry-leaders in almost every sector—and continue to thrive after 40+ years of change by operating with integrity. We know that true innovation starts when everyone is empowered to contribute. That’s why we’re committed to growing an inclusive workforce that promotes opportunities for all.Oracle careers open the door to global opportunities where work-life balance flourishes. We offer competitive benefits based on parity and consistency and support our people with flexible medical, life insurance, and retirement options. We also encourage employees to give back to their communities through our volunteer programs.We’re committed to including people with disabilities at all stages of the employment process. If you require accessibility assistance or accommodation for a disability at any point, let us know by emailing <a href="mailto:accommodation-request_mb@oracle.com" rel="nofollow" target="_blank">accommodation-request_mb@oracle.com</a> or by calling +1 888 404 2494 in the United States. Oracle is an Equal Employment Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability and protected veterans’ status, or any other characteristic protected by law. Oracle will consider for employment qualified applicants with arrest and conviction records pursuant to applicable law. <h4>Experience Level</h4>Mid Level

Oracle India Private Limited

Network Engineer

Infrastructure Engineering IIIYour role will be instrumental in shaping the future at one of the world's largest and most influential companies.As a member of our Infrastructure Platforms Engineering team, you will  join a high-performing team dedicated to developing and deploying large-scale infrastructure solutions that support JPMorgan Chase and Co.’s diverse and critical businesses. You'll be using the latest technologies, data management, and security practices in all aspects of Infrastructure and software development. Critical thinking, clear communication, and collaboration are key to successful product delivery. Job responsibilities<ul><li>Executes creative solutions for the design, development, and technical troubleshooting for problems of high complexity</li><li>Applies technical expertise and problem-solving methodologies to projects of large scope</li><li>Drives a work stream or project consisting of one or more infrastructure engineering technologies</li><li>Works with other platforms to architect and implement changes required to resolve issues and modernize the organization and its technology processes</li><li>Strongly considers upstream/downstream data and systems or technical implications and advises on mitigation actions</li><li>Adds to team culture of diversity, equity, inclusion, and respect</li><li>Flexible to work in off hours/weekends &amp; in 24x7 on-call rotation.</li></ul> Required qualifications, capabilities, and skills<ul><li>Formal training or certification on infrastructure engineering concepts and 3+ years applied experience</li><li>Very good understanding in multiple infrastructure technologies and protocols including Global and Local load balancing, DNS, network routing, switching, firewalls and proxies.</li><li>Good knowledge and understanding of REST/JSON, API implementation and container based technologies.</li><li>Experience with programmatic methods of network device interaction, configuration and lifecycle management.</li><li>Thorough understanding of business technology drivers and their impact on architecture design, performance and monitoring, best practices.</li><li>Strong critical-thinking and problem-solving skills with clear communication.</li><li>Ability to collaborate with different teams and roles to achieve common goals.</li><li>Hands on experience with Atlassian products such as JIRA, Bitbucket, and Confluence.</li><li>Advanced knowledge and experience with network load balancing in F5 Load balancing technology (GTM, LTM, ASM, APM, AFM)</li><li>Extensive experience working in operations and troubleshooting complex configuration or device issues in Load balancing.</li><li>Experience working in CLI (command line interface) </li></ul> Preferred qualifications, capabilities, and skills<ul><li>F5 Certifications will be preferred but not desirable, like BIG-IP TMOS Administration (201) and LTM Technology Specialist (301)</li><li>Proficient in one programming language (ex. Python) and automation framework (Ansible)</li><li>Ability to multi-task across project/initiatives and deliver according to time commitments</li><li>Experience with Infrastructure as Code – IaC implementation. </li></ul><h4>Experience Level</h4>Senior Level

JP Morgan Services India Pvt Ltd

Technical Engineer

Application Senior Engineer Skills Required:• Manage the assigned Application Projects/Workpackages• Define and update the Application project plan• Manage calibration datasets integration and evolution• Adopt calibration methodologies, procedures and tools shared byour team. Experience: 7-10 years Share your updated resume now.

SACHA Engineering

Senior Application Engineer

Senior Engineer – Core Wireless (Domain Expert) What you work:As a Senior Engineer you will be responsible for,<ul><li>Developing and maintaining high-quality software solutions for our 4G and 5G Mobile Packet core solutions</li><li>Collaborate with cross-functional teams to define, design, and ship new features</li><li>As a Senior Engineer you will be responsible to design and implement a new 3GPP functionality at a component level, independently</li></ul> Mandatory skills:<ul><li>Proficiency in any of the programming languages – C, C++, Go, JAVA</li><li>Should have hands on experience in building any of the core network elements in 4G/5G packet core or IMS networks</li><li>Strong problem-solving skills</li><li>Good design skills – Used design patterns in component development.</li></ul> Desired skills:<ul><li>Virtualisation/Cloud Native Architecture understanding</li><li>Scripting proficiency</li><li>Exposure to CI/CD frameworks, Automation</li></ul> &nbsp;Preferred Qualifications:<ul><li>Experience:&nbsp;4 to 6 yrs from Telecommunication or Networking background.</li><li>Education:&nbsp;B.Tech/BE (CSE/ECE) or any other equivalent degree&nbsp;</li></ul>

Tejas Networks Ltd

Senior Engineer

Staff Engineer-SSD Firmware Experience / Skills:<ul><li>In depth knowledge and extensive experience with embedded firmware development</li><li>Expertise in the use of scripting languages, programming tools and environments</li><li>Extensive experience programming in Python</li><li>Experience in the storage industry in SSD, HDD, storage systems, or a related technology</li><li>Understanding of storage interfaces including ideally PCIe/NVMe, SATA, or SAS</li><li>Experience with NAND flash and other non-volatile storage</li><li>Ability to work independently with a minimum of day-to-day supervision</li><li>Experience with team leadership and/or supervising junior engineers and technicians</li><li>Ability to work in a multi-functional team and under the pressure of multiple priorities</li></ul> Share your updated resume now.

Micron Technology Operations India Llp

Principle/ Sr Staff - Physical Design & PnR<h4>
 
 General Information
 </h4>






 Job Title
 

 Principle/ Sr Staff - Physical Design &amp; PnR
 



 Job ID
 

 8878
 



 Country
 

 India
 



 City
 

 Bengaluru
 



 Date Posted
 

 21-Jan-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 R&amp;D Engineering
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.<h4>You Are:</h4>You are a passionate and dedicated R&amp;D Staff Engineer with a deep understanding of physical design and a knack for solving complex design challenges. With a strong background in place &amp; route, timing closure, and power optimization, you thrive in dynamic environments where technological advancements are constant. Your expertise in low-power, high-performance design, especially with advanced nodes under 5nm, sets you apart. You are familiar with industry-leading tools like Fusion Compiler, Primetime, and Formality, and you bring a solid knowledge of scripting languages such as TCL, Perl, and Python. You hold a BS or MS in Electrical Engineering or a related field, with over 5 years of relevant experience. Your strong investigative and problem-solving skills, combined with your enthusiasm for learning new technologies, make you a perfect fit for our innovative team. Excellent communication skills in English, self-motivation, and a result-oriented mindset are essential traits you possess.<h4>What You’ll Be Doing:</h4><ul><li>Developing and implementing innovative methodologies for high-performance cores and IPs.</li><li>Collaborating with a global team to enhance PPA (Performance, Power, Area) metrics.</li><li>Utilizing advanced technologies and tools to improve design quality and process efficiency.</li><li>Contributing to both flow development and the implementation of complex IPs.</li><li>Addressing top-notch critical design challenges using Synopsys implementation tools.</li><li>Staying updated with the latest technology nodes and industry trends.</li></ul><h4>The Impact You Will Have:</h4><ul><li>Driving innovation in high-performance core and IP implementation methodologies.</li><li>Enhancing the efficiency and predictability of the implementation process.</li><li>Improving the quality of results through advanced technological applications.</li><li>Contributing to the development of cutting-edge semiconductor technologies.</li><li>Solving complex design challenges to achieve best-in-class PPA and TAT targets.</li><li>Supporting the continuous advancement of Synopsys' technological capabilities.</li></ul><h4>What You’ll Need:</h4><ul><li>Deep knowledge of physical design, place &amp; route, timing closure, and power optimization.</li><li>Experience in low-power, high-performance design and advanced nodes under 5nm.</li><li>Familiarity with Fusion Compiler, Primetime, and Formality.</li><li>Proficiency in scripting languages such as TCL, Perl, and Python.</li><li>A BS or MS in Electrical Engineering or a related field with 5+ years of relevant experience.</li></ul><h4>Who You Are:</h4><ul><li>Self-motivated, enthusiastic, and result-oriented.</li><li>Strong investigative and problem-solving skills.</li><li>Eager to learn and explore new technologies.</li><li>Excellent communication skills in English.</li><li>Knowledge of high-performance CPUs/GPUs and interface IP controllers like UCie, PCIe, USB is a plus.</li></ul><h4>The Team You’ll Be A Part Of:</h4>You will join a growing global team at Synopsys focused on advancing state-of-the-art high-performance cores/IPs implementation. This team is responsible for developing innovative methodologies to implement CPUs/GPUs and interface IPs that deliver more performance with less power. You will work with industry-leading Synopsys implementation tools and tackle the most complex design challenges, contributing to the continuous improvement of PPA metrics and the achievement of best-in-class targets.<h4>Rewards and Benefits:</h4>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Junior Designer

Sr. VLSI Design & Verification Engineer What we’re looking for: <ul><li> 5+ years of hands-on experience in RTL design or verification</li><li> Expertise in high-speed protocols (PCIe, USB, DDR, etc.)</li><li> Strong knowledge of SystemVerilog, UVM, and scripting languages</li><li> Experience with industry-standard EDA tools</li><li> Passion for innovation and problem-solving</li></ul> Share your updated resume now.

Scaledge

Sr Firmware Engineer <a rel="noopener noreferrer" href="\&quot;https://www.linkedin.com/search/results/all/?keywords=%23capgeminiengineering&amp;origin=HASH_TAG_FROM_FEED\&quot;" target="_blank">Capgemini Engineering</a> is hiring Sr Firmware Engineer&nbsp;Experience: 6–9 years Educational Qualifications: BE/ ME/ MS/BTech/MTech Electrical, Electronics , Computer Science Job Description:<ul><li>C/C++ programming</li><li>Embedded system development, Firmware, Device drivers &amp; Board support packages.</li><li>Knowledge of processor architectures – 8bit, 16bit and 32bit, DSPs</li><li>Knowledge of Software development life cycle – SDLC</li><li>Knowledge of Operating System concepts</li><li>Hands on experience on RTOS(GHS Integrity/VxWorks/ FreeRTOS) / Bare Metal Scheduler</li><li>Understand Firmware Architecture , Scheduler / Task manager implementations</li><li>Understand and Implement design represented by&nbsp;Finite State Machine (FSM), State Transition Matrix (STM), STD</li><li>Worked on atleast one full SDLC project/program</li><li>Capability to read hardware designs &amp; schematic.</li><li>Exposure to using oscilloscope, multi-meter.</li><li>Exposure to Industrial&nbsp;/ Medical standards (ISO 13485. IEC 62304, IEC 601010, IEC 61508)</li></ul>

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