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CAD Framing Checker <ul><li>Experience: 7+ Years</li><li>Skills: AISC PEMB Framing</li><li>Software: AutoCAD</li><li>2 Positions</li></ul> Share your resume now.

Cadeploy Engineering Private Limited

Mechanical Draftsman

STA Engineer Skills requried:• In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floorplanning, Power Grid Design, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification, Chip finishing. Should have experience on Physical Design Methodologies and lower technology nodes.• Should have experience on programming in Tcl/Tk/Perl to automate design process and improve efficiency.• Must have hands-on experience on PnR Suite from Synopsys/Cadence (Innovus, ICC2)• Strong experience on Static Timing Analysis (PrimeTime – SI), EM/IR-Drop analysis (PT-PX, Redhawk), Physical Verification (Calibre).• Understanding the practical application of methodologies and Physical Design Tools, Flow Automation and Improvements.• Experience in complex SOC integration, Low Power and High Speed Design and Advanced Physical Verification Techniques. Experience:&nbsp;3-8 Years

Modernize Chip Solutions

Associate Engineer

ISP Silicon Validation Engineer<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Computer Science, Electrical Engineering or equivalent practical experience. </li><li>3 years of experience with Computer Architecture.</li><li>Experience with C/C++, Python or Bash.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Master's degree in Computer Science, Electrical Engineering or equivalent practical experience.</li><li>Experience with software development tools, version control, compilers, and build tools.</li><li>Experience with hardware accelerators for camera multimedia systems.</li></ul><h4>About the job</h4>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.<h4>Responsibilities</h4><ul><li>Develop, and execute software tests to validate ISP blocks and integration.</li><li>Read hardware specifications, identify and develop test cases to run on Field-programmable Gate Array (FPGA) emulation and silicon.</li><li>Develop software test methodologies.</li><li>Support volume production through screening and characterization tests.</li><li>Support power measurements, correlation and debug.</li></ul><h4>Experience Level</h4>Mid Level

Google India Pvt Ltd

Testing Engineer

VP- Engineering Job Summary:We are looking for experienced VP- Engineering to provide sound technical leadership in all aspectsof our business. You will communicate with employees, clients, and customers to ensure ourcompany’s technologies are used appropriately.Strategic thinking and strong business acumen are essential in this role. We expect you to be wellversed in current technological trends and familiar with a variety of business concepts. If you are also an excellent communicator and public speaker Responsibilities:• Develop technical aspects of the company’s strategy to ensure alignment with its business goals• Discover and implement new technologies that yield competitive advantage• Help departments use technology profitably• Supervise system infrastructure to ensure functionality and efficiency• Build quality assurance and data protection processes Monitor KPIs and IT budgets to assess technological performance• Use stakeholders’ feedback to inform necessary improvements and adjustments to technology• Communicate technology strategy to partners and investors Requirements:• Proven experience in technology or similar leadership role• Knowledge of technological trends to build strategy• Understanding of budgets and business-planning• Ability to conduct technological analyses and research• Excellent communication skills• Leadership and organizational abilities• Strategic thinking• Problem-solving aptitude• B.Sc/B.Tech in Computer Science or a related field; MBA or other relevant graduate degree is a plus Experience:<ul><li>8+ years&nbsp;</li></ul>

BioQube

Senior Project Manager

Physical Design Engineer - Foundry Team As one of the largest R&amp;D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.&nbsp; ﻿Roles and Responsibilities<ul><li>Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA , timing and physical signoffs</li><li>Hands on experience doing physical design and timing closure of complex blocks and full-chip designs.</li><li>Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus.</li><li>Should have strong understanding of timing, power and area trade-offs and optimization of PPA.</li><li>Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities.</li><li>Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows.</li><li>Experience with large SOC designs (&gt;20M gates) with frequencies in excess of 1GHZ .</li><li>Expertise in block level and full-chip SDC clean up, Synthesis optimization , Low Power checking and logic equivalence checking.</li><li>Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling).</li><li>Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.</li><li>Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence.</li><li>Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.</li><li>Should have gone through recent successful SOC tape-outs.</li></ul> Experience – 5+ Years of experience Qualifications<ul><li>B.Tech/B.E/M.Tech/M.E</li></ul>

Samsung India Electronics Pvt Ltd 

Design Engineer

Hardware Design Engineer We are looking for talented Hardware Design Engineer to join our team. Experience: 4-9 YearsDescription• Experience in complete hardware design life cycle• Experince in schematic and bom generatin layout co-ordination.• Strong Knowledge of ASPICE for Hardware Engineering (HWE),• Understand EMI/EMC Standards• Knowledge of Standard like Functional Safety (Part-5 Hardware) ISO26262

L&T Technology Services Ltd

Hardware Engineer

Scada - Ignition Engineer We're hiring below position: Position: Scada - Ignition Engineer&nbsp;Experience: 4 to 6 years If you're interested, please share your profile.

Capgemini

Electrical / Electronics Engineer

Design for Test Engineer Job DescriptionWe are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with a minimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities<ul><li>Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans.</li><li>Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy.</li><li>Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&amp;R IP blocks for Scan, MBIST and other test interfaces.</li><li>Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing.</li><li>Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet.</li><li>Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs.</li><li>Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations.</li><li>Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types.</li><li>Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues.</li><li>Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs.</li><li>Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting.</li><li>Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow.</li><li>Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory.</li><li>Knowledge of LogicBIST with Test point insertion, X-blocking.</li><li>Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements.</li><li>Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug.</li><li>Ability to perform volume diagnostics on the parts to isolate and improve the patterns.</li></ul> Requirements<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design for Test.</li><li>Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows.</li><li>Prior experience working on IP level and SOC level DFT projects.</li><li>Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc.</li><li>Worked in full chip design or complex IP delivery in the area of DFT.</li><li>Experience in post silicon debug, diagnosis and yield enhancements is a plus.</li></ul>

Eximietas Design

Senior Test Engineer

Staff Engineer, VLSI Design Engineering<h4>Company Description</h4>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.<h4>Job Description</h4> Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes.Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirementsWork closely with team and actively participate in technical discussions and reviews.Pro-actively get design issues/problems solved.Contribute to or propose innovative design solutions and design methodologies. <h4>Qualifications</h4><ul><li>Bachelors/Masters degree in Electronics &amp; Telecommunication/Electrical engineering  (VLSI Design)</li><li>Hands-on design knowledge on both Digital custom, Analog &amp; mixed signal design environment.</li><li>4+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable.</li><li>NAND Flash Design knowledge is plus</li><li>Familiar with custom design methodology &amp; flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including  DLL, Rx, Tx and clocking circuits</li><li>Knowledge of High Speed layout guidelines, analog layout techniques, including floor-planning, matching, shielding and parasitic optimization</li><li>Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc..</li><li>Familiarity with package/board/Power integrity /signal integrity constraints is a plus.</li><li>Strong communication skills &amp; circuit design knowledge is preferred.</li><li>Tool knowledge: spice tools: finesim, hspice &amp; other flows</li><li>Good automation &amp; scripting knowledge is plus.</li></ul><h4>Additional Information</h4>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at <a href="mailto:jobs.accommodations@sandisk.com">jobs.accommodations@sandisk.com</a> to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. <h4>Experience Level</h4>Senior Level

SanDisk India Device Design Centre Pvt.Ltd

Embedded Systems Engineer

Optical Networks Integration Architect We're hiring Optical Networks Integration Architect Experience Required: 8–12 Years Key Skills &amp; Expertise<ul><li>EMS/NMS &amp; FCAPS in 4G/5G Optical Networks</li><li>DWDM/OTN configuration, mapping, cross-connects, protection/restoration</li><li>SNMP, Netconf, RESTAPI, CLI, XML/JSON, TMF</li><li>Python, Perl, C Programming | Linux/Unix</li><li>Kafka, Docker, Kubernetes, Helm</li><li>Tools: JDSU/SPIRENT, COM5, Arcsight, GitHub, JIRA</li><li>Integration with Huawei, Cisco, Juniper, Extreme Networks</li></ul> Optical Domain Knowledge<ul><li>OTN Mapping: Ethernet over OTN, ODU frames</li><li>Cross-Connects: OXC, digital switching</li><li>Performance Monitoring: Fault detection, latency tracking</li><li>DWDM Design: Channel spacing, transponder selection</li><li>Optical Components: Amplifiers (EDFA/Raman), ROADMs</li><li>Channel Provisioning: Laser power, attenuation, OTDR validation</li><li>Reference Guides: Cisco ONS 15454, Huawei NE40E</li></ul> Responsibilities<ul><li>Design &amp; develop Optical NMS integration architecture</li><li>Configure &amp; validate DWDM/OTN components</li><li>Automate deployment using Kubernetes, Helm, Docker</li><li>Conduct interoperability &amp; system testing</li><li>Collaborate with cross-functional teams (Transport/RAN, Cloud, DevOps)</li><li>Provide support during live deployments &amp; field trials</li><li>Create release documentation (MOP, ATP, Configuration Guide)</li></ul> Work on cutting-edge telecom infrastructure, collaborate with top engineers, and shape the future of optical network automation.If interested, Reach out with CV.

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Engineering - Hardware & Networks Jobs - 1514 Verified Vacancies