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Technical Program Manager – Physical DesignNVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for 30+ years. It’s an outstanding legacy of innovation that’s motivated by phenomenal technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, encouraging environment where everyone is inspired to do their best work. Come join our team and see how you can make a lasting impact on the world!We are seeking a highly organized and detail-oriented Physical Design Program Manager to lead and drive execution across complex ASIC/SoC development programs. This role will focus on coordinating internal teams, managing third-party contractors and vendors, and ensuring successful delivery of physical design projects against defined timelines and quality standards. In this role, the Technical Program Manager (TPM) will lead all block/chip level Physical Design (PD) activities, from floor planning to layout verification. This role also includes managing the netlist to GDSII flow, ensuring quality control, and coordinating with engineering teams and contractors. This role is critical for improving PPA and ensuring timely project execution.What you will be doing:<ul><li>Program Management: Drive end-to-end planning and execution of physical design programs, ensuring alignment with engineering goals, schedules, and deliverables.</li><li>Third-Party Contract Management: Oversee engagement with external contractors, ensure clear definition of scope, deliverables, and performance expectations.<ul><li>Streamline onboarding and deboarding processes for contractors.</li><li>Collect daily feedback from contractors to identify potential issues and areas for improvement.</li><li>Handle contractors' timesheets and ensure accuracy for billing and payment.</li><li>Manage contractors' paperwork, including contracts and agreements.</li><li>Manage contractor attrition and replacement, ensuring smooth transitions.</li><li>Frequently remind contractors about information security (infosec) matters.</li></ul></li><li>Vendor Management: Establish and maintain productive relationships with EDA vendors, IP providers, and service partners. Track deliverables, resolve issues, and escalate risks as needed.</li><li>Resource Management: Collaborate with engineering managers to allocate internal and external resources effectively, monitor utilization, and address capacity constraints.<ul><li>Work closely with engineering on various KPIs to improve overall execution processes and deliverables.</li><li>Collaborate with engineering and vendors to deliver and execute the roadmap.</li><li>Participate in sprint planning, stand-ups, sprint reviews, and retrospectives.</li></ul></li><li>Schedule Tracking: Develop and maintain detailed program schedules, track progress, and drive accountability across multiple stakeholders. Identify and mitigate risks proactively.</li><li>Cross-functional Coordination: Partner with design, verification, CAD, and operations teams to ensure seamless execution across all phases of the physical design flow.</li><li>Reporting &amp; Communication: Provide clear, concise program updates to leadership and stakeholders. Highlight risks, dependencies, and mitigation plans.</li><li>Physical Design Leadership: Lead all block/chip level PD activities, including floor plans, abstract view generation, RC extraction, PNR, STA, EM, IR DROP, DRCs, and schematic to layout verification. Collaborate with design teams to address design challenges. Debug tool/design related issues and improve RTL2GDS flow to enhance PPA. Oversee all aspects of physical design and implementation of GPU and other ASICs</li></ul>What we need to see:<ul><li>Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related discipline.</li><li>7+ years of experience in semiconductor industry, with at least 3+ years in program/project management roles.</li><li>Strong understanding of ASIC/SoC design flows, with emphasis on physical design processes.</li><li>Proven experience managing third-party contractors and vendor relationships.</li><li>Excellent organizational, analytical, and communication skills.</li><li>Strong ability to influence without authority and drive cross-functional alignment.</li><li>Familiarity with project management tools (e.g., MS Project, JIRA).</li><li>Familiarity with EDA tool licensing, vendor engagement models, and budget tracking</li><li>Preferred candidates with either PMP certification.</li></ul><h4>Experience Level</h4>Senior Level

Nvidia Graphics Pvt Ltd

Junior Project Engineer

Subcontractor<h4>Area(s) of responsibility</h4>JD - Windchill DeveloperResponsibilities:<ul><li>Configure, Customize &amp; Build solutions aligned with business process and requirements.</li><li>Develop applications using Windchill’s REST API, </li><li>Deploy and debug code through build process and with accordance to best practices throughout the development lifecycle.</li><li>Work closely with onshore/offshore Business/Solution Architects and support them in developing prototypes and implementing full solutions.</li><li>Understand the technical requirements and develop detailed design documents.</li><li>Coordinate support activities and identify solutions for complex issues.</li><li>Develop code with minimum supervision, that meets quality standards and best practices.</li><li>Provide unit and functional test-cases for the implemented solutions.</li></ul> Knowledge/Skills, Education, and Experience<ul><li>5-7 years of experience in configuring and customizing Windchill PLM and related modules</li><li>Ability to install, configure and upgrade Windchill and prior experience with integrations is a plus.</li></ul><h4>Experience Level</h4>Senior Level

Birlasoft Limited

Developer

EOIR EngineerResponsible for assembly and testing of Electro-Optical Infrared (EO/IR) system.


Responsible to develop the complete EOIR system


Responsible to carry out sensor bore-sighting.


Responsible to carry out Fine tuning of sensors and lens.


Responsible to conduct environmental tests for EOIR system.     


Responsible for field testing of system.


Hands-on experience on Laser test equipment’s like power meter, M2 measurement unit, beam profiler, thermal imager.



Bachelor's degree in Electronics/Mechanical/Opto electronics EngineeringExperience:<ul><li>Work experience as an EOIR System for min 5 years</li><li>Knowledge of Electro-Optical Infrared (EO/IR) Assembly.</li><li>Knowledge of sensor bore-sighting</li><li>Knowledge of Fine tuning of sensors and lens.</li><li>Hands-on experience on Laser test equipment’s like power meter, M2 measurement unit, beam profiler, thermal image</li></ul><h4>Experience Level</h4>Mid Level

Adani Enterprises Ltd

Engineer

Engineering Manager(Firmware), Systems TeamWe’re in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry.This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.SHOULD YOU ACCEPT THIS CHALLENGE...The DFM Firmware Team plays a crucial role in designing and developing the Direct Flash Module (DFM) – a key module of Pure's Flasharray and Flashblade enterprise storage solutions. The DFM is an internally designed enterprise storage device using the NAND flash technology. Compared with the off-the-shelf SSD, the DFM has the competitive advantage of  simplicity, high performance, low cost and scalability.As a leader of the DFM firmware team, you'll have rare opportunities to work across various domains, including the entire data path, NAND media management, and low-level hardware interfaces. Our firmware design enables us to quickly integrate the latest NAND technologies from various vendors. We were pioneers in adopting QLC for enterprise storage solutions, releasing the first QLC DFM in 2019. Our proprietary media management policies and algorithms position Pure as a leader in enabling QLC NAND in the enterprise storage industry.You'll work closely with the Purity software, hardware, NAND, and drive qualification teams. This offers a unique opportunity to learn the latest technologies, including the newest generations of NAND, NVMe/PCIe, as well as SSD controllers. Firmware development opens doors to experiences in embedded software design, hardware and system integration. You'll develop a comprehensive understanding and gain insights into the entire product development and release process.What You Will Be Doing…<ul><li>Project Management: Collaborate with program teams to manage firmware project schedules, deliverables, dependencies, risks, and resources effectively.</li><li>Agile Leadership: Lead the team sprints, set sprint goals, manage the backlog, and prioritize tasks to ensure efficient and iterative development.</li><li>Process Improvement: Continuously improve the firmware team productivity and engineering development processes to enhance product quality and development speed.</li><li>Team Development: Manage team performance, conduct 1-on-1 meetings, provide timely feedback, and contribute to the professional growth and development of team members.</li></ul>What You Bring To The Team...<ul><li>12+ years experience in SSD/Storage/Embedded domain along with excellent FW &amp; HW debug skills</li><li>3+ years of experience in technical leadership or management roles focused on embedded systems.</li><li>B.E. or M.E in Electrical Eng, Electronics &amp; Communication Eng, Computer Eng</li><li>Proficiency in C/C++ and Python programming languages.</li><li>Understanding of hardware-software interface; knowledge of SSD controllers or NAND is a plus.</li><li>Expertise in Agile development and continuous integration practices, with a track record of managing projects throughout the entire product development cycle.</li><li>Strong communication skills, both verbal and written, enabling effective collaboration with cross-functional teams and stakeholders.</li><li>Demonstrated analytical and problem-solving abilities, with a keen eye for detail and quality.</li><li>Proven ability to deliver projects to market on schedule and gather customer feedback for continuous improvement.</li></ul> <ul><li>We are primarily an in-office environment and therefore, you will be expected to work from the Banglaore office in compliance with Pure’s policies, unless you are on PTO, or work travel, or other approved leave.</li></ul>WHAT YOU CAN EXPECT FROM US:<ul><li>Pure Innovation: We celebrate those who think critically, like a challenge and aspire to be trailblazers.</li><li>Pure Growth: We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area™, Fortune's Best Workplaces for Millennials™ and certified as a Great Place to Work®!</li><li>Pure Team: We build each other up and set aside ego for the greater good.</li></ul>And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out <a href="http://purebenefits.com">purebenefits.com</a> for more information.ACCOMMODATIONS AND ACCESSIBILITY:Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at <a href="mailto:TA-Ops@purestorage.com">TA-Ops@purestorage.com</a> if you’re invited to an interview.OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM:We’re forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn’t just accepted but embraced. That’s why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership. Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.<h4>Experience Level</h4>Senior Level

Pure Storage India Pvt Ltd

Engineering Manager

Physical Design Engineer - Foundry Team As one of the largest R&amp;D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.&nbsp; ﻿Roles and Responsibilities<ul><li>Complex SOC Top Physical Implementation for next generation SOCs in area of mobile application processors, modem sub-systems and connectivity chips by means of Synthesis , Place and Route, STA , timing and physical signoffs</li><li>Hands on experience doing physical design and timing closure of complex blocks and full-chip designs.</li><li>Experience in top level floor planning including partition shaping and sizing, pin placement, channel planning, high speed signal and clock planning and feed-through planning is a plus.</li><li>Should have strong understanding of timing, power and area trade-offs and optimization of PPA.</li><li>Power user of industry standard tools (ICC/DC/PT/VSLP/Redhawk/Calibre/Formality) and able to understand their capabilities.</li><li>Should have solid understanding of scripting languages such as Perl/Tcl and implementation flows.</li><li>Experience with large SOC designs (&gt;20M gates) with frequencies in excess of 1GHZ .</li><li>Expertise in block level and full-chip SDC clean up, Synthesis optimization , Low Power checking and logic equivalence checking.</li><li>Familiar with deep sub-micron designs (8nm/5nm) and associated issues (manufacturability, power, signal integrity, scaling).</li><li>Familiar with typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block integration, and package interactions.</li><li>Familiar in hierarchical design, top-down design, budgeting, timing and physical convergence.</li><li>Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level.</li><li>Should have gone through recent successful SOC tape-outs.</li></ul> Experience – 5+ Years of experience Qualifications<ul><li>B.Tech/B.E/M.Tech/M.E</li></ul>

Samsung India Electronics Pvt Ltd 

Design Engineer

Chief EngineerJLL empowers you to shape a brighter way.  Our people at JLL and JLL Technologies are shaping the future of real estate for a better world by combining world class services, advisory and technology for our clients. We are committed to hiring the best, most talented people  and empowering them to  thrive, grow meaningful careers and to find a place where they belong.  Whether you’ve got deep experience in commercial real estate, skilled trades or technology, or you’re looking to apply your relevant experience to a new industry, join our team as we help shape a brighter way forward.   Roles &amp; Responsibility: -Roles &amp; Responsibility: -Critical Equipment Management:<ul><li>Hi Side Equipment Management</li></ul><ul><li>Lead the engineering team in evaluating, selecting, and acquiring cutting-edge semiconductor equipment.</li><li>Collaborate with vendors to assess equipment performance and plan upgrades for advanced technology adoption.</li><li>Implement strategies to enhance equipment reliability and reduce mean time to repair (MTTR).</li><li>Facilitate collaboration with vendors to ensure seamless integration of new equipment into the lab environment.</li></ul><ul><li>Scrubber Management</li></ul><ul><li>Develop and implement protocols for efficient operation and maintenance of scrubbers.</li><li>Conduct regular assessments to ensure scrubbers meet air quality standards.</li><li>Implement improvements to enhance the overall effectiveness of scrubber systems.</li></ul><ul><li>Toxic Gases Management</li></ul><ul><li>Develop and enforce strict protocols for the safe handling, storage, and disposal of toxic gases.</li><li>Conduct regular safety drills and training sessions for team members on handling toxic gases.</li><li>Collaborate with vendors to enhance gas detection systems and implement advanced safety features.</li></ul><ul><li>ETP Management</li></ul><ul><li>Optimize ETP performance to meet wastewater treatment standards and regulatory requirements.</li><li>Collaborate with environmental engineers to implement advanced technologies for ETP efficiency.</li><li>Implement preventive maintenance programs to minimize downtime and ensure continuous ETP operation.</li></ul><ul><li>Gas Panel Management</li></ul><ul><li>Collaborate in the design and optimization of gas panel systems for semiconductor processes.</li><li>Implement safety measures and protocols related to gas panel operation.</li><li>Train team members on gas panel operation and emergency procedures.</li></ul>Project &amp; Operation Management – <ul><li>Project Management</li></ul><ul><li>Lead complex projects such as lab expansions, infrastructure upgrades, and facility improvements.</li><li>Collaborate with architects, Designers, contractors, and other stakeholders for effective project execution.</li><li>Implement project management best practices, ensuring timely completion within budget constraints.</li></ul><ul><li>EHS Management</li></ul><ul><li>Oversee EHS initiatives within the engineering department, ensuring compliance and best practices.</li><li>Collaborate with EHS teams to integrate safety measures into engineering processes.</li><li>Implement measures to enhance the overall well-being and safety of engineering team members.</li></ul><ul><li>Vendor Management</li></ul><ul><li>Collaborate with vendors for equipment procurement, maintenance, and services, ensuring cost-effectiveness and quality.</li></ul><ul><li>Budget Management</li></ul><ul><li>Collaborate in budget planning, ensuring financial resources are allocated effectively for engineering projects.</li></ul><ul><li>Team Leadership</li></ul><ul><li>Provide strong leadership to a multidisciplinary team of engineers and technicians, fostering a culture of innovation and excellence.</li><li>Establish and communicate team goals aligned with the lab's strategic objectives.</li><li>Conduct performance evaluations and implement career development plans for team members.</li><li>Implement continuous improvement initiatives and recognize team achievements.</li></ul>Compliance &amp; Governance -<ul><li>Risk Management</li></ul><ul><li>Assess and manage risks associated with engineering projects, ensuring proactive risk mitigation measures.</li></ul><ul><li>Compliance &amp; Audits</li></ul><ul><li>Lead the development and implementation of robust safety protocols and compliance standards.</li><li>Stay abreast of industry standards and regulatory requirements, implementing necessary changes in protocols and procedures.</li><li>Interface with regulatory agencies to ensure the lab's compliance with environmental and safety regulations.</li></ul><ul><li>ESG Responsibilities</li></ul><ul><li>Integrate ESG considerations into the decision-making process for facility projects and operations.</li><li>Develop strategies to reduce the lab's environmental impact and promote social responsibility.</li><li>Implement measures to enhance diversity and inclusion within the engineering team and the lab.</li><li>Collaborate with cross-functional teams to incorporate ESG considerations into lab design and operations.</li></ul><ul><li>Regulatory Affairs</li></ul><ul><li>Monitor and ensure compliance with relevant regulations and standards governing engineering projects and lab operations.</li></ul><ul><li>Data Security and Intellectual Property Protection</li></ul><ul><li>Collaborate with IT and security teams to ensure data security and intellectual property protection measures are in place.</li></ul>Energy, Innovation &amp; Quality – <ul><li>Energy Efficiency and Sustainability</li></ul><ul><li>Integrate energy-efficient solutions into engineering projects, promoting sustainability in lab operations.</li><li>Implement strategies to improve energy efficiency and enhance sustainability.</li><li>Lead the adoption of innovative technologies in engineering projects.</li></ul><ul><li>Emergency Response and Continuity Planning</li></ul><ul><li>Implement and test emergency response plans for engineering projects, minimizing disruptions.</li></ul><ul><li>Collaboration with Research and Development Teams</li></ul><ul><li>Collaborate with R&amp;D teams to align engineering projects with research goals and facilitate seamless integration.</li></ul><ul><li>Space Utilization and Optimization</li></ul><ul><li>Collaborate in lab design and layout planning to optimize space utilization for engineering projects and team efficiency.</li></ul><ul><li>Innovation and Technology Adoption</li></ul><ul><li>Advocate for the adoption of innovative technologies in engineering projects, keeping the lab at the forefront of industry advancements.</li></ul><ul><li>Quality Management</li></ul><ul><li>Incorporate quality management practices into engineering processes to deliver high-quality results and meet industry standards.</li></ul>Standards, Community, and Training –<ul><li>International Standards (ISO)</li></ul><ul><li>Ensure compliance with ISO standards applicable to engineering practices, contributing to the lab's overall certification efforts.</li></ul><ul><li>Community Engagement</li></ul><ul><li>Represent the lab in community engagement initiatives and promote a positive image through outreach and collaboration.</li></ul><ul><li>Training and Development</li></ul><ul><li>Provide ongoing training for engineering team members to enhance skills and keep them informed about technological advancements.</li></ul>Execution of Safety Protocols -<ul><li>Strict adherence to cleanroom protocols to minimize contamination.</li><li>Comprehensive training on the proper handling, storage, and disposal of chemicals.</li><li>Regular equipment inspections and maintenance to ensure safe operation.</li><li>Implementation of lockout/tagout procedures to prevent accidental equipment activation during maintenance.</li><li>Mandating the use of appropriate PPE, including safety glasses, face shields, gloves, and specialized protective clothing.</li><li>Development and regular testing of emergency response plans for various scenarios.</li><li>Installation of gas detection systems to monitor and alert personnel to the presence of toxic gases.</li><li>Regular calibration and maintenance of gas monitoring equipment.</li><li>Comprehensive training programs on safety procedures, chemical hazards, and emergency response.</li><li>Ongoing education to keep employees informed about the latest safety protocols and industry best practices.</li><li>Access to and understanding of Material Safety Data Sheets (MSDS) for all chemicals used in the semiconductor manufacturing process.</li><li>Collaboration with regulatory agencies to ensure compliance with environmental and safety regulations.</li><li>Implementation of advanced air filtration and ventilation systems to maintain a clean and safe working environment.</li><li>Monitoring and regular maintenance of air quality control systems.</li><li>Adherence to specific safety guidelines for handling semiconductor manufacturing tools.</li><li>Proper training on tool operation and maintenance.</li><li>Implementation of continuous improvement programs to identify and address safety concerns.</li><li>Regular safety audits and reviews to enhance overall safety performance.</li></ul>Qualifications:<ul><li>Minimum requirement: B-Tech/BE (Mechanical/Electrical/Civil &amp; Environmental engineering)</li><li>Preferred: - Master’s or Ph.D. in a related engineering field.</li><li>Additional Qualification –</li></ul><ul><li>Substantial experience in health care Manufacturing or R&amp;D labs in Pharmaceutical or semiconductor Industry.</li><li>Certifications in facility management, project management, environmental management may be advantageous.</li></ul>Location: On-site –Bengaluru, KAScheduled Weekly Hours:48If this job description resonates with you, we encourage you to apply even if you don’t meet all of the requirements.  We’re interested in getting to know you and what you bring to the table!JLL Privacy NoticeJones Lang LaSalle (JLL), together with its subsidiaries and affiliates, is a leading global provider of real estate and investment management services. We take our responsibility to protect the personal information provided to us seriously. Generally the personal information we collect from you are for the purposes of processing in connection with JLL’s recruitment process. We endeavour to keep your personal information secure with appropriate level of security and keep for as long as we need it for legitimate business or legal reasons. We will then delete it safely and securely.For more information about how JLL processes your personal data, please view our <a href='\"https://www.us.jll.com/en/careers/candidate-privacy-statement\"' target='\"_blank\"'>Candidate Privacy Statement</a>.For additional details please see our career site pages for each country.For candidates in the United States, please see a full copy of our Equal Employment Opportunity and Affirmative Action policy <a href='\"https://www.us.jll.com/en/careers/disclaimers\"' target='\"_blank\"'>here</a>.Jones Lang LaSalle (“JLL”) is an Equal Opportunity Employer and is committed to working with and providing reasonable accommodations to individuals with disabilities.  If you need a reasonable accommodation because of a disability for any part of the employment process – including the online application and/or overall selection process –  you may contact us at <a href='\"http://link.jll.com/Accommodation_Requests\"' target='\"_blank\"'>Accommodation Requests</a>. This email is only to request an accommodation. Please direct any other general recruiting inquiries to our <a href='\"https://www.us.jll.com/en/contact-us\"' target='\"_blank\"'>Contact Us</a> page &gt; I want to work for JLL.

Jones Lang Lasalle Property Consultants India Pvt Ltd

Chief Engineer

Principal Engineer We are hiring Principal Engineer (Network Domain)<ul><li>Location: Bangalore (Work from Office)</li><li>Notice period: Immediate joiners up to 60 days</li><li>Experience : 10+years</li></ul> Share your updated cv to <a rel="noopener noreferrer" href="\&quot;mailto:neetika_yadav@onwardgroup.com\&quot;" target="_blank">neetika_yadav@onwardgroup.com</a>

Onward Technologies Limited

Silicon Micro-architecture and RTL Lead , Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.</li><li>10 years of experience in ASIC development with Verilog/SystemVerilog, Vhsic Hardware Description Language (VHDL).</li><li>Experience in micro-architecture and design IPs and Subsystems.</li><li>Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).</li></ul> <h4>Preferred qualifications:</h4><ul><li>Experience with scripting languages (e.g., Python or Perl).</li><li>Experience in SoC designs and integration flows.</li><li>Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies..</li><li>Knowledge of high performance and low power design techniques.</li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.<h4>Responsibilities</h4><ul><li>Drive development of Complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization.</li><li>Own micro-architecture and implementation of IPs and subsystems.</li><li>Work with Architecture, Firmware and Software teams to drive feature closure and develop micro-architecture specifications.</li><li>Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Identify and drive Power, Performance and Area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Senior Level

Google India Pvt Ltd

Embedded Systems Engineer

Silicon Networking RTL Design Senior Engineer, Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.</li><li>8 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.</li><li>Experience with ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).</li><li>Experience in micro-architecture and design of IPs and subsystems in Networking domain such as packet processing, bandwidth management, congestion control, etc.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Experience with scripting languages (e.g., Python or Perl).</li><li>Experience in SoC designs and integration flows.</li><li>Knowledge of high performance and low power design techniques.</li><li>Knowledge of bus architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.</li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.In this role, you will be part of a team developing ASICs used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You'll solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The ML, Systems, &amp; Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.<h4>Responsibilities</h4><ul><li>Own microarchitecture and implementation of complex IPs and subsystems in the Networking domain.</li><li>Work with Architecture, Firmware, and Software teams to drive feature closure and develop micro-architecture specifications. </li><li>Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Identify and lead power, performance, and area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Senior Level

Electronic Engineer

Linux Device Driver Developer Capgemini is hiring for Linux Device Driver Developer (LDD) can join in 30 Days, and possess the required skill set, apply to this job. Experience: 4- 10 years Key Requirements:1. 3-5 Yrs of experience in Embedded Linux Kernel/Drivers domain2. Embedded Software development and porting on Linux and ARM platforms3. Strong Programming skills on C &amp; Data Structures4. Expertise on OS (Memory Mgmt, Scheduling, IPC, Multi-threading/processing)5. Experience in Linux Kernel/Device Drivers6. Proficiency in debugging embedded systems, including using tools like JTAG7. Understanding of System architecture and debugging at a system level. Please send your resume with the following details:Subject Line: Job Application- LDD (Linux Device Drivers)Name:Total Exp:Rel exp:Current CTC:ECTC:Current location:Are you willing to relocate?Notice period/ LWD:

Capgemini

Linux Engineer

ASIC RTL Design Engineer Capgemini is hiring for below role: Position: ASIC RTL Design EngineerExperience: 5+yrsLocation: Bangalore .Note: Considering only ASIC experience candidates. Interested candidate share profile via email.

Capgemini Engineering

STA Engineer Capgemini is hiring for below role: Position: STA EngineerExperience: 5+yrsLocation: Bangalore . Interested candidate share profile via email.

Associate Engineer

Principal Hardware Development Engineering<h4>Company Description</h4>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.<h4>Job Description</h4>We are seeking a Principal Hardware Development Engineer to join our innovative team in Bangalore , India. In this l role, you will drive the development of cutting-edge hardware solutions, guiding projects from concept to production.<ul><li>Lead and mentor a team of hardware engineers, fostering innovation and technical excellence</li><li>Develop and implement hardware architecture strategies aligned with product roadmaps</li><li>Oversee the entire hardware development lifecycle, from initial concept to mass production</li><li>Collaborate with cross-functional teams to ensure seamless integration of hardware and software components</li><li>Conduct technical reviews and provide expert guidance on complex hardware design challenges</li><li>Establish and maintain best practices for hardware development processes and methodologies</li><li>Evaluate new technologies and components to enhance product performance and competitiveness</li><li>Manage relationships with key vendors and external partners</li><li>Contribute to intellectual property development and patent applications</li></ul><h4>Qualifications</h4><ul><li>Master's degree in Electrical Engineering or related field with 10+ years of experience in hardware development and leading complex projects</li><li>Advanced knowledge of hardware design principles, PCB design, and high-speed interfaces (e.g., PCIe, UFS, LPDDR)</li><li>Expertise in CAD tools, simulation software, and lab equipment (oscilloscope, TDR, VNA)</li><li>Strong understanding of electrical engineering principles and manufacturing processes</li><li>Proven ability to lead and mentor engineering teams, with excellent project management skills</li><li>Outstanding analytical, problem-solving, communication, and interpersonal skills</li><li>Experience in product lifecycle management and semiconductor/consumer electronics industry preferred</li><li>Ability to adapt to rapidly changing technologies and market demands</li></ul><h4>Additional Information</h4>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at <a href="mailto:jobs.accommodations@sandisk.com">jobs.accommodations@sandisk.com</a> to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.<h4>Experience Level</h4>Senior Level

SanDisk India Device Design Centre Pvt.Ltd

Associate Hardware Engineer

CATIA DMU Technical Lead Job Description-&nbsp;Cabin, MSI, ESI, Catia 3D /2D/ F3DPosition&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;: Technical Lead (2B)Experience&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;: 6 to 8 yearsPrimary Skills : Cabin, MSI, ESI, AIRBUS PMT ( CATIA V5, VPM, Trend, Full 3D etc.), DMU knowledge, Configuration Management basicsEducation: B.E./ B.Tech. (Aeronautical, Mechanical) Roles and Responsibilities<ol><li>3D Model &amp; Assembly checks in aircraft DMU &amp; against set of requirements</li><li>2D Drawing checks against set of requirements</li><li>3D model &amp; assembly design, compilation and integration</li><li>Interface alignment</li><li>2D Drawing creation (Interface, specification and installation drawings)</li><li>Full 3D Dataset compilation</li><li>Equipment steering</li><li>Operational configuration management</li><li>Functional electrics (PD, WD, FD creation and modification)</li><li>Creation and modification of customized specifications</li><li>2D to 3D conversion</li><li>Responsible for performing DMU(Digital Mock-up) Integration, design and F3D activities using AIRBUS&nbsp;methodologies.</li><li>Full 3D experience in Cabin , ESI and MSI</li><li>Good experience in DMU QC0, QC1, QC2 activities</li><li>A good team member who is responsible for supporting AIRBUS projects in DMU/M&amp;T bundles</li><li>Accountable for activity execution, closing of assigned responsibilities/activities and capable of keeping effective communication with all the stakeholders</li><li>Capture best practices, build knowledge repository &amp; training materials to train new team members added into the project team</li><li>Proactive in idea generation, innovation mindset to improve product, process methods and tools</li><li>Create quick PoC (Proof of Concepts) or build new solution proposal for various platforms</li></ol> Detailed Candidate Profile / Required Skills:<ol><li>Must have minimum of 6+ years of experience in AIRBUS&nbsp;Process, Methods and Tools and Full 3D.</li><li>Hands on experience in CATIA V5/V6, PASS SSI, Enovia VPM, TreND, Context Builder, CADint, Taksy, Gilda, DPDS and Optegra will be preferred.</li><li>Hands on experience in 3DExperience platform (functional) would be an advantage.</li><li>Sound knowledge in AIRBUS&nbsp;product structure and Configuration management process.</li><li>Should have a good technical knowledge of Aircraft Structures, Systems, Cabin &amp; Cargo Layouts.</li><li>Experience in Design and Quality check of AIRBUS Structural, Systems and Cabin/Interior components will be preferred.</li><li>Prior experience in SA and A350 projects and knowledge in AIRBUS functional tool testing environments would be preferred.</li><li>Preferable to have basic knowledge in Agile / SAFe methodologies.</li><li>Ability to work with cross-functional teams, flexible and agile enough to meet the expected deliverables to achieve common business goals &amp; objectives.</li><li>Very good communication, good interpersonal skills (excellent attitude to collaborate, support each other, willingness to learn from all and to develop relationships with team members, customers and all stakeholders) and create positively thriving environment within the team/organization</li></ol> QualificationsB Tech , BE

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