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Design Verification Lead We are hiring for below - Role: Design Verification LeadExperience: 7+ yearsLocation: Bangalore If interested, you can share profile.

Capgemini

Assistant Design Engineer

ASIC RTL Design Lead We are hiring for below - Role: ASIC RTL Design LeadExperience: 7+ yearsLocation: Bangalore If interested, you can share profile.

Embedded Systems Engineer

Full Stack Architect <ul><li>Lead innovation with Vue.js, Node.js, Python, and cloud-native tools like Docker, Kubernetes, Helm, and Kafka.</li><li>Build high-performance, scalable applications, design APIs, and manage multi-environment deployments.</li><li>Short joiners preferred</li></ul> Share your updated resume now.

Live Connections

Full Stack Engineer

FPGA Design Engineer Job Descriptions &amp; RequirementsFPGA Design Engineer will be working on our existing and next generation Protocol Analysers and similar products.• Opportunity to develop a new product to top 10 semiconductor companies to test their next generation products• The role involves contributing to the entire FPGA based product development flow starting from requirement analysis till final product testing in lab environment.• The candidate will be responsible for architecture/micro-architecture design and implementation of the logic in Verilog for targeted FPGA, writing test benches to validate the design etc.• Job involves frequent interaction with board design, software, testing and lab teams to deliver the product meeting the customer requirements.• Job involves understanding and working with interfaces such as PCIe, GigE, MPHY/UFS, DPHY/CSI/DSI, USB, SD, eMMC, I3C/I2C, SPI/QSPI etc.• Contributing to/participating in internal design reviews to ensure adherence to the company FPGA design process. Requirement:Experience in designing and implementing FPGA based solution in Xilinx or Altera FPGA, preferably FPGA based product development experience.• Must have experience in System Design with Xilinx/Altera FPGA devices with relevant tools.• Must have experience in Verilog and/or VHDL coding.• Must have experience in using constraints to achieve timing requirement.• Experience in working on high speed FPGA designs is a major plus.• Thorough knowledge of Static Timing Analysis (STA) is an added advantage.• Must have experience in building test bench for verification.• knowledge in any of the protocols like UFS, UniPro, USB, Ethernet, PCIe, I3C, I2C, SPI, QSPI, UART, JTAG, SPMI, RFFE, SD, eMMC etc.• Must have hands on experience with FPGA debugging tools and test &amp; measurement instruments such as oscilloscope and Logic Analyzer.• Should have strong problem solving and debugging skills. ﻿Experience:&nbsp;3-10 Years

Modernize Chip Solutions

ASIC Physical Design Tools Flows & Methodology Lead THE ROLE:&nbsp;As a Silicon Design Engineer in the AMD AECG ASIC TFM (tools Flows Methodology) team, you will work with design experts (FE and BE) to come up with the best implementation methodologies/flows and work on development and support of the FE/BE flows.&nbsp;KEY RESPONSIBILITIES:&nbsp;<ul><li>Define and drive key Frontend/Beckend/Physical Design methodologies.</li><li>Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows.</li><li>Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug.</li><li>Work closely with design teams to gather requirements and develop strategies to tackle key technical problems.</li><li>Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC &amp; LVS), Crosstalk Analysis, EM/IR</li><li>Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk</li></ul>&nbsp;PREFERRED EXPERIENCE:&nbsp;<ul><li>8+ years of professional experience in physical design, preferably with high performance designs.</li><li>Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.</li><li>Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.</li><li>Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery</li><li>Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation</li><li>Versatility with scripts to automate design flow.</li><li>Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams</li><li>Excellent physical design and timing background.</li><li>Strong analytical/problem solving skills and pronounced attention to details.</li></ul>

Amd India Private Limited

Embedded Software Developer

Embedded Windows Driver Developer SKILL SET• 4+ years in Windows driver development, preferably with AMD or similar x86 platforms.• Strong experience in Windows networking driver development.• Experience in Windows kernel-mode driver development (WDM, KMDF, UMDF). • Proficiency in C/C++ and debugging tools (WinDbg, TraceView).• Experience in analyzing and debugging kernel crash dumps (WinDBG).• Familiarity with PCle enumeration, device ID handling, and WHQL certification processes. • Experience with Ethernet MAC/PHY integration and redriver configuration. Experience - 4-10 years Share your updated resume now.

Scaledge

IP/SOC Verification Engineer We are hiring for experienced IP/SOC Verification Engineers with 5+ years in PCIe (Gen5, Gen6), DDR, and Ethernet protocols.If you have a passion for cutting-edge verification and want to be part of innovative projects, let’s connect! Share your updated resume now.

Testing Engineer

Sr. VLSI Design & Verification Engineer What we’re looking for: <ul><li> 5+ years of hands-on experience in RTL design or verification</li><li> Expertise in high-speed protocols (PCIe, USB, DDR, etc.)</li><li> Strong knowledge of SystemVerilog, UVM, and scripting languages</li><li> Experience with industry-standard EDA tools</li><li> Passion for innovation and problem-solving</li></ul> Share your updated resume now.

Android BSP Developer SKILL SET• Engineer with 4+ years of experience in Android Framework /HAL/ driver development• Strong C/C++ development skills with a good understanding of object-oriented design• Good understanding of Android framework, overall Android Architecture.• Proficient in any one of Android HAL amongst Audio, Graphics, Camera, Power etc.• Desirable experience with Multimedia framework such as OpenMAX, Codec2.• Compliance to CTS/VTS and support in resolving defects• Preferable exposure to Machine learning, Deep Learning• Strong background in embedded systems development System knowledge, System Debugging. KEY WORDS:• Embedded, Android, HAL, Audio, Video, Camera, Graphics, Framework, OpenMax, Codec2, ALSA, CTS, 12S, Tensorflow • Experience: 4+ Years• Qualification: Bachelors or Master's in Computer Science, Engineering, Mathematics• Notice Period: Immediate to 30 Days Share your updated resume now.

Android Developer

Verification Engineer – PCIe Expert Are you a Verification Engineer with deep expertise in PCIe protocol and a passion for building high-performance systems? Join our innovative team and work on next-gen silicon solutions that power tomorrow’s technology. Experience: 4+ yearsSpecialization: PCIe Protocol Verification Share your updated resume now.

CATIA DMU Module Lead Job Description-&nbsp;Catia DMU, CABIN, ESI, MSI, Catia 3D /2D/ F3DPosition: Module Lead (2A)Primary Skills : Cabin, MSI, ESI, AIRBUS PMT ( CATIA V5, VPM, Trend, Full 3D etc.), DMU knowledge, Configuration Management basicsEducation: B.E./ B.Tech. (Aeronautical, Mechanical)Total Experience Expected: 04-06 years Roles and Responsibilities<ol><li>3D Model &amp; Assembly checks in aircraft DMU &amp; against set of requirements</li><li>2D Drawing checks against set of requirements</li><li>3D model &amp; assembly design, compilation and integration</li><li>Interface alignment</li><li>2D Drawing creation (Interface, specification and installation drawings)</li><li>Full 3D Dataset compilation</li><li>Equipment steering</li><li>Operational configuration management</li><li>Functional electrics (PD, WD, FD creation and modification)</li><li>Creation and modification of customized specifications</li><li>2D to 3D conversion</li><li>Responsible for performing DMU(Digital Mock-up) Integration, design and F3D activities using AIRBUS&nbsp;methodologies.</li><li>Full 3D experience in Cabin , ESI and MSI</li><li>Good experience in DMU QC0, QC1, QC2 activities</li><li>A good team member who is responsible for supporting AIRBUS projects in DMU/M&amp;T bundles</li><li>Accountable for activity execution, closing of assigned responsibilities/activities and capable of keeping effective communication with all the stakeholders</li><li>Capture best practices, build knowledge repository &amp; training materials to train new team members added into the project team</li><li>Proactive in idea generation, innovation mindset to improve product, process methods and tools</li><li>Create quick PoC (Proof of Concepts) or build new solution proposal for various platforms</li></ol>&nbsp;Detailed Candidate Profile / Required Skills:<ol><li>Must have minimum of 4+ years of experience in AIRBUS&nbsp;Process, Methods and Tools and Full 3D.</li><li>Hands on experience in CATIA V5/V6, PASS SSI, Enovia VPM, TreND, Context Builder, CADint, Taksy, Gilda, DPDS and Optegra will be preferred.</li><li>Hands on experience in 3DExperience platform (functional) would be an advantage.</li><li>Sound knowledge in AIRBUS&nbsp;product structure and Configuration management process.</li><li>Should have a good technical knowledge of Aircraft Structures, Systems, Cabin &amp; Cargo Layouts.</li><li>Experience in Design and Quality check of AIRBUS Structural, Systems and Cabin/Interior components will be preferred.</li><li>Prior experience in SA and A350 projects and knowledge in AIRBUS functional tool testing environments would be preferred.</li><li>Preferable to have basic knowledge in Agile / SAFe methodologies.</li><li>Ability to work with cross-functional teams, flexible and agile enough to meet the expected deliverables to achieve common business goals &amp; objectives.</li><li>Very good communication, good interpersonal skills (excellent attitude to collaborate, support each other, willingness to learn from all and to develop relationships with team members, customers and all stakeholders) and create positively thriving environment within the team/organization</li></ol>

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Engineering Hardware Networks Jobs In Kalyan - 1955 Verified Vacancies

Assistant Design Engineer

Embedded Systems Engineer

Full Stack Engineer

Embedded Systems Engineer

Embedded Software Developer

Embedded Systems Engineer

Testing Engineer

Testing Engineer

Embedded Systems Engineer

Embedded Systems Engineer

Android Developer

Testing Engineer

Testing Engineer

Programmer Analyst