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Design for Test Engineer Job DescriptionWe are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with a minimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities<ul><li>Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans.</li><li>Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy.</li><li>Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&amp;R IP blocks for Scan, MBIST and other test interfaces.</li><li>Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing.</li><li>Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet.</li><li>Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs.</li><li>Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations.</li><li>Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types.</li><li>Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues.</li><li>Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs.</li><li>Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting.</li><li>Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow.</li><li>Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory.</li><li>Knowledge of LogicBIST with Test point insertion, X-blocking.</li><li>Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements.</li><li>Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug.</li><li>Ability to perform volume diagnostics on the parts to isolate and improve the patterns.</li></ul> Requirements<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design for Test.</li><li>Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows.</li><li>Prior experience working on IP level and SOC level DFT projects.</li><li>Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc.</li><li>Worked in full chip design or complex IP delivery in the area of DFT.</li><li>Experience in post silicon debug, diagnosis and yield enhancements is a plus.</li></ul>

Eximietas Design

Senior Test Engineer

Senior Standard Cell Designer<h4>
 
 General Information
 </h4>






 Job Title
 

 Senior Standard Cell Designer
 



 Job ID
 

 8804
 



 Country
 

 India
 



 City
 

 Hyderabad
 



 Date Posted
 

 17-Jan-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 R&amp;D Engineering
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

<h4 id="isPasted">Alternate Job Titles:</h4><ul><li>Senior Cell Library Design Engineer</li><li>Senior Logic Library Design Engineer</li><li>Senior Standard Cell Designer</li></ul><h4>We Are:</h4>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.<h4>You Are:</h4>You are an experienced Standard Cell Library Design Engineer with a passion for innovation and technology. You hold a Bachelor's or Master's degree from a reputable university and have over three years of experience in designing standard cell libraries. Your expertise extends to optimizing standard cell circuits to achieve superior performance, power, and area (PPA). You have designed complex circuits such as flip-flops, clock gating cells, level shifters, and power gating cells. Your deep understanding of CMOS device characteristics and design rules in submicron process nodes, especially in FINFET/GAA technologies, sets you apart. You are proficient in running high sigma variation analysis and have a knack for layout design and optimization. Your analytical and logical skills are exemplary, and you thrive in a collaborative environment, working effectively with geographically distributed R&amp;D teams. If you are driven by innovation and eager to contribute to groundbreaking technology, we want to meet you.<h4>What You’ll Be Doing:</h4><ul><li>Designing and optimizing standard cell libraries to achieve targeted PPA.</li><li>Developing complex circuits including flip-flops, clock gating cells, level shifters, and power gating cells.</li><li>Collaborating with layout designers to optimize layout parasitics.</li><li>Engaging in layout extraction and understanding layout-dependent parameters.</li><li>Conducting timing and power characterization of standard cells.</li><li>Working closely with cross-functional teams for optimization across the design chain.</li></ul><h4>The Impact You Will Have:</h4><ul><li>Enhancing the performance, power, and area of standard cell libraries.</li><li>Contributing to the development of high-impact, cutting-edge technology.</li><li>Driving innovation in complex circuit design and optimization.</li><li>Ensuring the successful integration of IP blocks into SoCs.</li><li>Influencing the design and development of self-driving cars, AI, and IoT devices.</li><li>Supporting Synopsys’ leadership in the silicon IP market.</li></ul><h4>What You’ll Need:</h4><ul><li>Bachelor's or Master's degree in Electrical Engineering or related field.</li><li>3+ years of experience in standard cell library design.</li><li>Expertise in CMOS device characteristics and submicron process nodes.</li><li>Proficiency in designing complex circuits and running high sigma variation analysis.</li><li>Experience in layout design and optimization.</li></ul><h4>Who You Are:</h4><ul><li>Strong analytical and logical thinker.</li><li>Detail-oriented with excellent problem-solving skills.</li><li>Effective communicator and collaborator.</li><li>Innovative and passionate about technology.</li><li>Adaptable and able to work in a dynamic, fast-paced environment.</li></ul><h4>The Team You’ll Be A Part Of:</h4>You will join the Logic Library Group, a dynamic team focused on developing high-performance standard cell libraries. The team collaborates closely with other R&amp;D groups to optimize the entire design chain and deliver cutting-edge technology solutions. Together, you will work on innovative projects that drive the future of chip design and integration.<h4>Rewards and Benefits:</h4>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Synopsys India Pvt Ltd

Electrical Design Engineer

Simulation Engineer Skills - Python / C++, URDF/XACRO, Kinematics, RTOSExperience - 2+ year Please Note:We will connect only with candidates whose profiles closely match our requirements and budget.

Delhivery

Design And Development Engineer

CATIA DMU Technical Lead Job Description-&nbsp;Cabin, MSI, ESI, Catia 3D /2D/ F3DPosition&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;: Technical Lead (2B)Experience&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;: 6 to 8 yearsPrimary Skills : Cabin, MSI, ESI, AIRBUS PMT ( CATIA V5, VPM, Trend, Full 3D etc.), DMU knowledge, Configuration Management basicsEducation: B.E./ B.Tech. (Aeronautical, Mechanical) Roles and Responsibilities<ol><li>3D Model &amp; Assembly checks in aircraft DMU &amp; against set of requirements</li><li>2D Drawing checks against set of requirements</li><li>3D model &amp; assembly design, compilation and integration</li><li>Interface alignment</li><li>2D Drawing creation (Interface, specification and installation drawings)</li><li>Full 3D Dataset compilation</li><li>Equipment steering</li><li>Operational configuration management</li><li>Functional electrics (PD, WD, FD creation and modification)</li><li>Creation and modification of customized specifications</li><li>2D to 3D conversion</li><li>Responsible for performing DMU(Digital Mock-up) Integration, design and F3D activities using AIRBUS&nbsp;methodologies.</li><li>Full 3D experience in Cabin , ESI and MSI</li><li>Good experience in DMU QC0, QC1, QC2 activities</li><li>A good team member who is responsible for supporting AIRBUS projects in DMU/M&amp;T bundles</li><li>Accountable for activity execution, closing of assigned responsibilities/activities and capable of keeping effective communication with all the stakeholders</li><li>Capture best practices, build knowledge repository &amp; training materials to train new team members added into the project team</li><li>Proactive in idea generation, innovation mindset to improve product, process methods and tools</li><li>Create quick PoC (Proof of Concepts) or build new solution proposal for various platforms</li></ol> Detailed Candidate Profile / Required Skills:<ol><li>Must have minimum of 6+ years of experience in AIRBUS&nbsp;Process, Methods and Tools and Full 3D.</li><li>Hands on experience in CATIA V5/V6, PASS SSI, Enovia VPM, TreND, Context Builder, CADint, Taksy, Gilda, DPDS and Optegra will be preferred.</li><li>Hands on experience in 3DExperience platform (functional) would be an advantage.</li><li>Sound knowledge in AIRBUS&nbsp;product structure and Configuration management process.</li><li>Should have a good technical knowledge of Aircraft Structures, Systems, Cabin &amp; Cargo Layouts.</li><li>Experience in Design and Quality check of AIRBUS Structural, Systems and Cabin/Interior components will be preferred.</li><li>Prior experience in SA and A350 projects and knowledge in AIRBUS functional tool testing environments would be preferred.</li><li>Preferable to have basic knowledge in Agile / SAFe methodologies.</li><li>Ability to work with cross-functional teams, flexible and agile enough to meet the expected deliverables to achieve common business goals &amp; objectives.</li><li>Very good communication, good interpersonal skills (excellent attitude to collaborate, support each other, willingness to learn from all and to develop relationships with team members, customers and all stakeholders) and create positively thriving environment within the team/organization</li></ol> QualificationsB Tech , BE

Sopra Steria India Limited

Technical Team Lead

Firmware Engineer We’re Hiring: Firmware EngineerExperience: 6–10 Years )Type: Full-time | On-site What You’ll Do:<ul><li>Collaborate with a multidisciplinary team to design, integrate, qualify, and test applications.</li><li>Implement innovative software algorithms and data structures.</li><li>Create detailed design and engineering documentation.</li><li>Conduct testing, debugging, and validation of functional modules.</li><li>Provide post-development support and contribute to system optimization.</li><li>Stay current with firmware development trends and methodologies.</li></ul> What You Bring:<ul><li>Proficiency in C/C++ and Assembly programming</li><li>Hands-on experience with RTOS and Embedded Linux</li><li>Strong knowledge of ARM, PIC, AVR microcontrollers</li><li>Expertise in debugging tools like JTAG, oscilloscopes, logic analyzers</li><li>Familiarity with communication protocols (UART, SPI, I2C, CAN)</li><li>Solid circuit design fundamentals and low-level driver development</li><li>Experience with Git and ability to read hardware schematics</li><li>Excellent problem-solving and testing skills</li></ul> If building robust, low-level firmware excites you — send your resume to <a rel="noopener noreferrer" href="\&quot;mailto:deepak.sagrawal@ascendion.com\&quot;" target="_blank">deepak.sagrawal@ascendion.com</a>

Ascendion Engineering Private Limited

Embedded Software Developer

FEA Engineer We're hiring below position: Position: FEA EngineerExperience: 6 to 9 yearsLocation: Bangalore If you're interested, please share your profile.

Capgemini

Mechanical Engineer (Refining)

Telematics Validation & Automation Engineer * 3-5 Years of Experience* Powertrain* Provetech* ECU Test Tool (Tracetronic)* Python. Notice Period: Immediate to 15 Days Only Send your application to <a rel=\"noopener noreferrer\" href=\"mailto:ajay.ms@ust.com\" target=\"_blank\">ajay.ms@ust.com</a>

UST Global

Automation Process Engineer

Consultant - Fatigue & Damage Tolerance Engineer Capgemini is hiring below position:- Designation: Consultant Experience: 4–6 Years Job Skill: Fatigue &amp; Damage Tolerance Engineer Location: Bengaluru Note: Please mention the Designation while sharing your CV for reference.To apply, please email your CV.

Fabrication Quality Engineer

EIS Engineer Role OverviewWe’re looking for a skilled EIS Engineer with a strong background in Medical Device Regulations and Control Systems Design &amp; Development (CSI). This is an exciting opportunity to work on end-to-end product development and ensure compliance with international standards. Key Responsibilities<ul><li>Lead and contribute to control system design and development for medical devices.</li><li>Ensure compliance with regulatory standards like FDA, ISO 13485, IEC 62304, etc.</li><li>Collaborate with cross-functional teams (hardware, software, QA, RA).</li><li>Prepare and maintain technical documentation for audits and approvals.</li><li>Support risk management, verification &amp; validation, and system integration.</li></ul> Requirements<ul><li>6–8 years of experience in EIS, medical device development, or control systems engineering.</li><li>Strong understanding of control systems (CSI) methodologies and tools (e.g., MATLAB/Simulink, LabVIEW, PLCs).</li><li>In-depth knowledge of medical device regulations and standards.</li><li>Excellent analytical, documentation, and communication skills.</li><li>BE/BTech or higher in Electronics, Instrumentation, Biomedical, or related fields.</li></ul> Share your updated resume now.

Teamware Solutions

Technical Operations Associate

LDD Developer We're hiring below position: Position: LDD DeveloperExperience: 6+ yearsLocation: Bangalore If you're interested, please share your profile.

Developer

WLAN Test Engineer Experience: 4+ YearsThis job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job OverviewAs a WLAN Test Engineer, your primary responsibility is to assess the functionality and performance of wireless networks/Devices. This includes conducting various tests to verify the network's speed, coverage, security, and overall reliability. You'll collaborate with Developers and quality assurance teams to identify and resolve any issues that may arise during testing. Additionally, you may be involved in designing test plans, executing test cases, analysing test results. Job Description<ul><li>Develop and execute test plans and test cases to assess WLAN performance, reliability, and security.</li><li>Conduct manual and automated tests to validate network configurations, protocols, and features.</li><li>Perform regression testing to ensure that new changes or updates do not adversely affect network functionality.</li><li>Identify, isolate, and document defects or issues found during testing, and work closely with development teams to resolve them.</li><li>Collaborate with cross-functional teams to understand product requirements and provide input on design and implementation considerations.</li><li>Utilize testing tools and equipment to simulate real-world network scenarios and assess performance under different conditions.</li><li>Analyze test results and provide detailed reports to stakeholders, including recommendations for network optimization and improvement.</li><li>Stay updated on industry trends, best practices, and emerging technologies related to WLAN</li><li>testing and network management.</li></ul> Qualifications<ul><li>Bachelor’s degree in Computer Science, Information Technology, Electrical Engineering, or a related field.</li><li>Proven experience in WLAN testing, network testing, or a similar role.</li><li>Proficiency in network protocols such as TCP/IP, UDP, DHCP, DNS, and HTTP.</li><li>Strong understanding of wireless networking technologies, including Wi-Fi standards (802.11a/b/g/n/ac/ax), RF fundamentals, and WLAN security protocols (WPA, WPA2, WPA3).</li><li>Familiarity with network testing tools and equipment such as traffic generators, protocol analyzers, spectrum analyzers, and wireless sniffers.</li><li>Experience with Android tools and devices is preferred.</li><li>Excellent analytical and problem-solving skills, with the ability to troubleshoot complex network issues.</li><li>Effective communication skills, with the ability to collaborate with cross-functional teams and communicate technical concepts to non-technical stakeholders.</li><li>Detail-oriented approach with a commitment to producing high-quality work and delivering accurate test results.</li></ul>

Associate Network Engineer

Design Verification Engineer This job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job OverviewWe are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description<ul><li>Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.</li><li>Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM</li><li>Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.</li><li>Analyze and implement System Verilog assertions and coverage (code, toggle, functional).</li><li>Provide mentorship and technical guidance to junior verification engineers.</li><li>Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.</li><li>Ensure verification signoff criteria are met and documentation is comprehensive.</li><li>Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.</li><li>Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.</li><li>Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.</li></ul> Qualifications<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>Master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design Verification.</li><li>Expertise in UVM (Universal Verification Methodology) and System Verilog.</li><li>Prior experience working on IP level and SOC level verification projects.</li><li>Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).</li><li>Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.</li><li>Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.</li><li>Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Proficiency in scripting languages such as shell, Makefile, and Perl.</li><li>Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.</li><li>C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.</li></ul>

Assistant Design Engineer

Senior Analog Layout Engineer Experience - 4-6 years Please share your CV at <a rel=\"noopener noreferrer\" href=\"mailto:prasad.adakambarribabu@moschip.com\" target=\"_blank\">prasad.adakambarribabu@moschip.com</a>

MosChip Technology Ltd

Electronic Engineer

Analog Design Engineer Job Descriptions &amp; RequirementsModernize Chip Solutions Pvt. Ltd is growing rapidly and is searching for experienced candidates for the position of Analog designerIn this role you would have the following responsibilities:• Ensure Analog sub-block performance adheres to SerDes standards and architecture document specifications.• Identify and refine circuit implementations to achieve optimal power, area and performance targets.• Propose design and verification strategies that efficiently use simulator features to ensure highest quality design• Oversee physical layout to minimize the effect of parasitics, device stress and process variation• Present simulation data for peer review• Ownership of Analog and mixed-signal building block that is integrated as part of a larger SerDes design• Document design features and test plans Experience:• 3 to 8 years of experience in SerDes/High-Speed Analog design and all Analog blocks like low dropout regulator, bandgap reference, voltage to current converter• Familiarity with transistor level circuit design of fundamental Analog and mixed -signal building blocks• Sound CMOS design fundamentals• Silicon-proven experience implementing circuits for Analog and mixed-signal building blocks• Design experience with some of the following SerDes sub-circuits: receiver equalizers, data samplers, voltage/current-mode drivers, serializers, LDOs, Bandgap, ADC/DAC, PLLs,DLLs

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