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Design Verification Engineer What We’re Looking For:<ul><li> Strong DV knowledge with C and System Verilog test development exposure</li><li> Experience with Gate Level Simulations</li><li> Hands-on with ARM-based SoCs</li><li> Knowledge of Power Aware Verification (UPF based RTL simulation)</li><li>Experience: 4–5 Years</li></ul> Share your updated resume now.

Digicomm Semiconductor

Assistant Design Engineer

Lead Design Verification Expert Skills:• System Verilog, UVM, SVA • MAC Protocol (Must) • SOC/ASIC/IP verification • PCIe, DDR, USB, DFT awareness, and leadership/mentoring. Experience: 5+ years (7+ preferred) Share your updated resume now.

Teamcenter/PLM ArchitectWe are seeking a highly skilled Senior Software Engineer with a strong background in Product Lifecycle Management (PLM) systems and cloud-based solutions. The ideal candidate will have extensive experience with Java/Spring Boot, microservices architecture, and cloud platforms, particularly Google Cloud Platform (GCP). Proficiency in NOSQLDB is also required.Strong knowledge in PLM Teamcenter Architecture, Customization (ITK, SOA, RAC and AWC) and configurations. Design and build scalable microservices using Java/Spring Boot.Leverage Google Cloud Platform (GCP) to deploy, manage, and optimize cloud-based applications.Utilize MongoDB for data storage, ensuring optimal performance and reliability.Collaborate with cross-functional teams to integrate PLM systems with other enterprise applications.Participate in the full software development lifecycle, including requirements gathering, design, development, testing, and deployment.Troubleshoot and resolve technical issues, providing timely and effective solutions.Strong knowledge in PLM Teamcenter Architecture, Customization (ITK, SOA, RAC and AWC) and configurations. Design and build scalable microservices using Java/Spring Boot.Leverage Google Cloud Platform (GCP) to deploy, manage, and optimize cloud-based applications.Utilize MongoDB for data storage, ensuring optimal performance and reliability.Collaborate with cross-functional teams to integrate PLM systems with other enterprise applications.Participate in the full software development lifecycle, including requirements gathering, design, development, testing, and deployment.Troubleshoot and resolve technical issues, providing timely and effective solutions.<h4>Experience Level</h4>Senior Level

Ford Motor

Senior Software Engineer

AMS Verification Engineer What We’re Looking For:<ul><li> Strong expertise in AMS verification methodologies</li><li> Hands-on experience with Verilog-AMS, SystemVerilog, and SPICE</li><li> Familiarity with mixed-signal co-simulation and analog behavioral modeling</li><li> Experience working on complex SoCs / IPs involving analog-digital interfaces</li><li> Exposure to UPF/CPF-based power verification is a plus</li><li>Experience: 8+ Years</li></ul> Share your updated resume now.

QA/QC Engineer

Verification Engineer<h1> </h1>Experience:&nbsp;4-10 YearsJob Descriptions &amp; RequirementsYou should have prior knowledge and experience with UVM verification and UVM environment development Additional responsibilities include:• Help develop test plan definition and development• Micro-architecture design verification, RTL verification, and documentation• Top-level and block-level performance verification, power, and use-case verification; and• Support test program development, chip validation, and chip life until production maturity.• Team Management and Building• Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development. Qualifications :• Experience in UVM verification and UVM environment development (must have)• Proficient in test plan definition and testcase development in C/Assembly/System Verilog Expertise

Modernize Chip Solutions

Testing Engineer

Emulation Engineer We are hiring for below skills.Role: Emulation Engineer with ZebuExperience: 5+ yearsLocation: Bangalore If Interested, please share resume.

Capgemini

Embedded Systems Engineer

Consultant - Electromechanical Engineer Capgemini is Hiring below role: Designation: ConsultantSkill: Electromechanical Engineer Experience: 4–6 Years ﻿If interested Send your CV: Mention the Role Title in the subject line.

Technical Consultant

Design Verification Lead We are hiring for below - Role: Design Verification LeadExperience: 7+ yearsLocation: Bangalore If interested, you can share profile.

Memory /Custom Layout Design Professional We are hiring for \"Memory /Custom Layout Design\". Requirement<ul><li>Sound knowledge &amp; hands on experience in Finfet technology, layout design and DRC limitations.</li><li>Proficient in physical verification flow &amp; debug, like DRC, LVS, ERC, Boundary conditions.</li></ul> Location: BangaloreExperience: 3 to 9years. If interested, you can share resume.

Mechanical CAD Designer

ASIC RTL Design Lead We are hiring for below - Role: ASIC RTL Design LeadExperience: 7+ yearsLocation: Bangalore If interested, you can share profile.

Full Stack Architect <ul><li>Lead innovation with Vue.js, Node.js, Python, and cloud-native tools like Docker, Kubernetes, Helm, and Kafka.</li><li>Build high-performance, scalable applications, design APIs, and manage multi-environment deployments.</li><li>Short joiners preferred</li></ul> Share your updated resume now.

Live Connections

Full Stack Engineer

FPGA Design Engineer Job Descriptions &amp; RequirementsFPGA Design Engineer will be working on our existing and next generation Protocol Analysers and similar products.• Opportunity to develop a new product to top 10 semiconductor companies to test their next generation products• The role involves contributing to the entire FPGA based product development flow starting from requirement analysis till final product testing in lab environment.• The candidate will be responsible for architecture/micro-architecture design and implementation of the logic in Verilog for targeted FPGA, writing test benches to validate the design etc.• Job involves frequent interaction with board design, software, testing and lab teams to deliver the product meeting the customer requirements.• Job involves understanding and working with interfaces such as PCIe, GigE, MPHY/UFS, DPHY/CSI/DSI, USB, SD, eMMC, I3C/I2C, SPI/QSPI etc.• Contributing to/participating in internal design reviews to ensure adherence to the company FPGA design process. Requirement:Experience in designing and implementing FPGA based solution in Xilinx or Altera FPGA, preferably FPGA based product development experience.• Must have experience in System Design with Xilinx/Altera FPGA devices with relevant tools.• Must have experience in Verilog and/or VHDL coding.• Must have experience in using constraints to achieve timing requirement.• Experience in working on high speed FPGA designs is a major plus.• Thorough knowledge of Static Timing Analysis (STA) is an added advantage.• Must have experience in building test bench for verification.• knowledge in any of the protocols like UFS, UniPro, USB, Ethernet, PCIe, I3C, I2C, SPI, QSPI, UART, JTAG, SPMI, RFFE, SD, eMMC etc.• Must have hands on experience with FPGA debugging tools and test &amp; measurement instruments such as oscilloscope and Logic Analyzer.• Should have strong problem solving and debugging skills. ﻿Experience:&nbsp;3-10 Years

Lead Engineer – 3GPP What you work:<ul><li>As a technical member, you will contribute in product development and delivery including planning, requirement analysis in wireless communication.&nbsp;</li><li>Analyze and prioritize various features for different sub-systems to get a synchronized system delivery in a phased manner&nbsp;</li><li>Will be looking after product simulation and other research-oriented functions&nbsp;</li><li>As a lead engineer, you will be responsible for leading a team and guiding them for optimum output.&nbsp;</li></ul> Mandatory skills:&nbsp;<ul><li>MTech/MS/PhDs from ECE/EE/CSE&nbsp;</li><li>Have made contribution to 3GPP CT&nbsp;</li><li>Have worked with MATLAB and/or Python simulation&nbsp;</li><li>Worked in 3GPP Release 17, 18 and attended 3GPP meetings&nbsp;&nbsp;</li><li>Thesis or present area of work in Rel 19 topics of CT#3, CT#4,SA#2&nbsp;</li></ul> Desired skills:&nbsp;<ul><li>Worked with any of the simulation tools.&nbsp;</li><li>Strong knowledge in wireless communication&nbsp;</li><li>Should be willing to travel Twice per quarter nationally/internationally&nbsp;&nbsp;</li><li>Mandatory to have done basic wireless communication, Computer&nbsp;</li></ul> Preferred Qualifications:&nbsp;<ul><li>Experience:&nbsp;6 to 9 years’ experience from Telecommunication background.&nbsp;</li><li>Education:&nbsp;MTech/MS/PhDs from ECE/EE/CSE</li></ul>

Tejas Networks Ltd

Sales Engineer

ASIC Physical Design Tools Flows & Methodology Lead THE ROLE:&nbsp;As a Silicon Design Engineer in the AMD AECG ASIC TFM (tools Flows Methodology) team, you will work with design experts (FE and BE) to come up with the best implementation methodologies/flows and work on development and support of the FE/BE flows.&nbsp;KEY RESPONSIBILITIES:&nbsp;<ul><li>Define and drive key Frontend/Beckend/Physical Design methodologies.</li><li>Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows.</li><li>Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug.</li><li>Work closely with design teams to gather requirements and develop strategies to tackle key technical problems.</li><li>Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC &amp; LVS), Crosstalk Analysis, EM/IR</li><li>Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk</li></ul>&nbsp;PREFERRED EXPERIENCE:&nbsp;<ul><li>8+ years of professional experience in physical design, preferably with high performance designs.</li><li>Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications.</li><li>Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction.</li><li>Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery</li><li>Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation</li><li>Versatility with scripts to automate design flow.</li><li>Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams</li><li>Excellent physical design and timing background.</li><li>Strong analytical/problem solving skills and pronounced attention to details.</li></ul>

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