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Post Silicon Validation- Staff Engineer<h4>
 
 General Information
 </h4>






 Job Title
 

 Post Silicon Validation- Staff Engineer
 



 Job ID
 

 12456
 



 Country
 

 India
 



 City
 

 Bhubaneswar
 



 Date Posted
 

 05-Aug-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 R&amp;D Engineering
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced and highly motivated individual with a passion for technology and innovation. You have a strong technical background in RTL, Physical Design, and post-silicon test and testability development. Your expertise in debugging and developing Process, Voltage, Temperature, Current, and Droop sensors is unparalleled. You thrive in a dynamic environment and excel in communication, teamwork, and leadership. You are eager to learn and contribute to the development of state-of-the-art PVT IP sensors that are integral to the silicon lifecycle monitoring process. You possess a mindset geared towards meticulous IP debug and documentation, ensuring the highest standards of product development and performance. What You’ll Be Doing: <ul><li>Serving as the single point of contact for post-silicon debug activities. </li><li>Enabling Product Requirement Documents (PRDs). </li><li>Working to enable IP as a product development platform. </li><li>Handling hands-on post-silicon test setups. </li><li>Collaborating on top-level physical design, board-level, and package-level designs. </li><li>Developing post-silicon reports and conducting debug analysis. </li></ul>The Impact You Will Have: <ul><li>Driving the successful development and deployment of PVT IP sensors. </li><li>Enhancing the reliability and performance of Synopsys' silicon lifecycle monitoring solutions. </li><li>Ensuring high-quality product development through meticulous testing and debugging. </li><li>Contributing to the continuous innovation in chip design and software security. </li><li>Supporting Synopsys' leadership in the market for PVT IP developments. </li><li>Empowering the creation of high-performance silicon chips used in various advanced technologies. </li></ul>What You’ll Need: <ul><li>Hands-on experience in post-silicon test setups. </li><li>Sound knowledge of Digital/AMS chip design and post-silicon debug. </li><li>BS or MS degree in Electrical Engineering with 5+ years of experience. </li><li>Understanding of top-level physical design, board-level, and package-level designs. </li><li>Expertise in RTL development and physical design.</li></ul>Who You Are:<ul><li>Strong communicator with excellent teamwork and interpersonal skills. </li><li>Detail-oriented with a mindset geared towards IP debug and documentation. </li><li>Proactive learner with the ability to adapt to new IP functionalities. </li><li>Highly motivated and capable of mentoring both internal teams and external customers.</li></ul>  The Team You’ll Be A Part Of: You will be part of the rapidly expanding PVT IP group at Synopsys, focusing on the development of cutting-edge PVT IP sensors. This team is dedicated to conceptualizing, designing, and productizing state-of-the-art sensors that play a critical role in the silicon lifecycle monitoring process. Collaborate with a group of innovative and highly skilled professionals to drive the future of technology.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Synopsys India Pvt Ltd

Testing Engineer

Silicon Design Verification Engineer, TPU, Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering or equivalent practical experience. </li><li>4 years of experience with verification methodology such as Universal verification methodology (UVM). </li><li>2 years of experience in the verification of IP designs such as IP, SoC, vector CPUs, etc. </li><li>Experience with SystemVerilog, SVA, and functional coverage. </li></ul> <h4>Preferred qualifications:</h4><ul><li>Master's degree in Electrical Engineering or a related field. </li><li>Experience with industry-standard simulators, revision control systems, and regression systems. </li><li>Experience with the full verification life cycle. </li><li>Experience in Artificial Intelligence/Machine Learning (AI/ML) Accelerators or vector processing units. </li><li>Excellent problem solving and communication skills. </li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.In this role, you will own the full verification life cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification. The ML, Systems, &amp; Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.<h4>Responsibilities</h4><ul><li>Plan the verification of digital design blocks and interact with design engineers to identify important verification scenarios.</li><li>Identify and write all types of coverage measures for stimulus and corner-cases. </li><li>Debug tests with design engineers to deliver functionally correct design blocks. </li><li>Measure to identify verification holes and to show progress towards tape-out. </li><li>Create a constrained-random verification environment using SystemVerilog and Universal verification methodology (UVM). </li></ul><h4>Experience Level</h4>Mid Level

Google India Pvt Ltd

Senior Architect . We need Sr Architect with US Project experience, with experience in single-family homes and US building codes. . Working Environment: 5 Days. Immediate availability is a strong advantage.. Location - Sohini Tech Park, 6, 7, 10th Floors, Nanakramguda Village, Gachibowli, Hyderabad, Telangana, 500032 Share your CV with the position mentioned.

Latinem Private Limited 

Senior Architect

Analog Design Engineer Job Descriptions &amp; RequirementsModernize Chip Solutions Pvt. Ltd is growing rapidly and is searching for experienced candidates for the position of Analog designerIn this role you would have the following responsibilities:• Ensure Analog sub-block performance adheres to SerDes standards and architecture document specifications.• Identify and refine circuit implementations to achieve optimal power, area and performance targets.• Propose design and verification strategies that efficiently use simulator features to ensure highest quality design• Oversee physical layout to minimize the effect of parasitics, device stress and process variation• Present simulation data for peer review• Ownership of Analog and mixed-signal building block that is integrated as part of a larger SerDes design• Document design features and test plans Experience:• 3 to 8 years of experience in SerDes/High-Speed Analog design and all Analog blocks like low dropout regulator, bandgap reference, voltage to current converter• Familiarity with transistor level circuit design of fundamental Analog and mixed -signal building blocks• Sound CMOS design fundamentals• Silicon-proven experience implementing circuits for Analog and mixed-signal building blocks• Design experience with some of the following SerDes sub-circuits: receiver equalizers, data samplers, voltage/current-mode drivers, serializers, LDOs, Bandgap, ADC/DAC, PLLs,DLLs

Modernize Chip Solutions

Electronic Engineer

Sr Verification Engineer<h1> </h1>Experience:&nbsp;4-10 YearsAs a Verification Engineer, you will play a crucial role in the development of next-generation Storage Networking ASICs. Your primary responsibilities will include:• Develop a detailed micro-architecture for both module-level and system-level test benchesVerification Micro-Architecture &amp; Documentation:• Produce comprehensive documentation outlining verification strategies and approaches.Firmware and Hardware Co-Simulations:• Conduct co-simulations to ensure seamless integration and functionality between firmware and hardware components.Test Plan Development:• Create detailed test plans, outlining methodologies and criteria for effective verification.Test Bench Coding and Test Writing:• Develop and code test benches, and write tests to validate module-level and system-level functionalities.Debugging:• Troubleshoot and resolve simulation failures at both module and system levels.RTL Code Coverage Analysis and Enhancements:• Analyze RTL code coverage to identify gaps and propose enhancements to improve verification coverage.Scripting for Automation:• Develop scripts to automate various aspects of the verification process, enhancing overall productivity and efficiencyValidation Support:• Assist in FPGA and ASIC validation processes, which includes analyzing Ethernet and PCIe traces and detailed hardware logging during system operation Requirement:• Graduation with 3+ years of hands-on code development experience• A degree in EE, CE, or CS

Senior Verification Engineer Skills: UVM, System Verilog, PCIe, DDR, Ethernet, USB, NVMe, UPF, MIPI, CXLExperience - 5+ yearsAvailability: Immediate to 60 Days Share your updated resume now.

Scaledge

Junior Test Engineer

GLS engineer We are looking for GLS engineer with 5+yrs of experience for Bangalore location. Brief JD:<ul><li>Total experience (5 -7 years) with SOC GLS experience of minimum 3+ years</li><li>hands on experience in GLS (Zero Delay, SDF, PAGLS)</li><li>Excellent debugging skills and fixing issues</li><li>Knowledge in SV/UVM and test bench flow</li><li>Good experience in EDA tools such as Synopsys Verdi, Cadence NC Sim.</li><li>Understanding of SOC Architecture</li></ul> If interested, please share your profile.

Capgemini Engineering

Engineer

System Testing & Commissioning Engineer We are Hiring at <a rel="noopener noreferrer" href="\&quot;https://www.linkedin.com/company/l&amp;t-technology-services-limited/\&quot;" target="_blank">L&amp;T Technology Services</a>. Role - System Testing &amp; Commissioning EngineerNotice - Immediate -30 DaysThe ideal candidate should have experience in Metro rail telecom Systems like CCTV, Master clock, Telephone, Fots, System Engineering / T&amp;C. Description<ul><li>Telecommunication systems testing and commissioning FOTS CCTV Clock Radio Telephone systems and Cyber security Etc.</li><li>Identification and management of technical risks in accordance with the Project management process.</li><li>Lead system design of respective system assigned, as per approved design plan</li><li>Define the overall subsystem design including BOQ, system performance parameters, test plans, of the sub-system. System design inputs, requirements finalization.</li></ul> Experience<ul><li>5 years in similar work experience is mandatory</li><li>B-Tech ECE/EEE</li><li>Experience 7-10 Years</li></ul>

L&T Technology Services Ltd

Test Engineer

Engineering Manager, Home Infrastructure, Platform and Devices<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree or equivalent practical experience.</li><li>8 years of experience in software development.</li><li>3 years of experience in a technical leadership role; overseeing projects.</li><li>2 years of experience in a people management, supervision/team leadership role.</li><li>Experience building distributed systems at a large scale.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Master’s degree or PhD in Engineering, Computer Science, or a related technical field.</li><li>3 years of experience working in a complex, matrixed organization.</li><li>Experience working with C++ or JAVA.</li></ul><h4>About the job</h4>Like Google's own ambitions, the work of a Software Engineer goes beyond just Search. Software Engineering Managers have not only the technical expertise to take on and provide technical leadership to major projects, but also manage a team of Engineers. You not only optimize your own code but make sure Engineers are able to optimize theirs. As a Software Engineering Manager you manage your project goals, contribute to product strategy and help develop your team. Teams work all across the company, in areas such as information retrieval, artificial intelligence, natural language processing, distributed computing, large-scale system design, networking, security, data compression, user interface design; the list goes on and is growing every day. Operating with scale and speed, our exceptional software engineers are just getting started -- and as a manager, you guide the way. With technical and leadership expertise, you manage engineers across multiple teams and locations, a large product budget and oversee the deployment of large-scale projects across multiple sites internationally. Voice Serving team develops scalable and trustworthy infrastructure to serve journeys triggered by voice and other modalities. We work across multiple areas of the serving stack including understanding, ranking and multi-modal fulfilment. We are constantly evolving our stack to blend the latest technological advances in Artificial Intelligence (AI) to elevate the quality of response to queries. The infrastructure we build ultimately enables highly differentiated experiences across various platforms and surfaces within Google Home.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world.<h4>Responsibilities</h4><ul><li>Support the design, architecture, and optimization of core functionalities such as query understanding, intent generation, and response planning across voice and other modalities for Agentic flows.</li><li>Assume ownership of the technical roadmaps for multiple Google Home programs.</li><li>Engage closely with cross-functional teams (e.g., infrastructure, intelligence, platform, experience) to ensure alignment.</li><li>Provide technical guidance to both junior and executive engineers, fostering a high-performance environment.</li><li>Demonstrate adaptability and a willingness to undertake new issues to address evolving team requirements.</li></ul><h4>Experience Level</h4>Senior Level

Engineering Manager

Analog Layout Engineer What We’re Looking For:<ul><li> Strong experience in analog layout design</li><li> Exposure to lower technology nodes (preferred)</li><li> Experience with tools like Virtuoso and Calibre</li><li> Good understanding of matching, shielding, and parasitic optimization techniques</li></ul> <ul><li>Experience: 4 to 10+ Years</li><li>Notice Period: Immediate to 30 Days</li></ul> Share your updated resume now.

Digicomm Semiconductor

IP/SOC Verification Engineer We are hiring for experienced IP/SOC Verification Engineers with 5+ years in PCIe (Gen5, Gen6), DDR, and Ethernet protocols.If you have a passion for cutting-edge verification and want to be part of innovative projects, let’s connect! Share your updated resume now.

CAD Framing Checker <ul><li>Experience: 7+ Years</li><li>Skills: AISC PEMB Framing</li><li>Software: AutoCAD</li><li>2 Positions</li></ul> Share your resume now.

Cadeploy Engineering Private Limited

Mechanical Draftsman

BSP Developer Key Skills:&nbsp;◾ BSP (Board Support Package) Development&nbsp;◾ Embedded Systems Programming&nbsp;◾ Diag, USB, Storage, PMIC&nbsp;◾ Expertise in Clock Management, Buses &amp; Peripherals&nbsp;◾ Strong Knowledge of Memory Management in Embedded Systems Experience: 3 – 5 Years Share your updated resume now.

MosChip Technology Ltd

Developer

Senior Designer, CAD EngineeringAbout Analog DevicesAnalog Devices, Inc. (NASDAQ: <a href="http://finance.yahoo.com/q?s=ADI" rel="noopener noreferrer" target="_blank">ADI</a> ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at <a href="https://www.analog.com/" rel="noopener noreferrer" target="_blank">www.analog.com</a> and on <a href="https://www.linkedin.com/company/analog-devices/posts/?feedView=all" rel="noopener noreferrer" target="_blank">LinkedIn</a> and <a href="https://x.com/adi_news" rel="noopener noreferrer" target="_blank">Twitter (X)</a>.          The Engineering Enablement organization is responsible for developing tools, methodologies, and providing support to engineering teams to accelerate product development across the company. As part of the Analog Tools &amp; Technology group within EE organization, this experienced CAD engineer shall develop and maintain CAD tools and methodologies used in Analog, RF and Mixed-Signal product development across the company. As an individual contributor, this engineer will be expected to possess necessary programming skills and circuit design knowledge to develop, QA, support, and enhance the EDA tools and associated infrastructure used by product development teams. Key responsibilities:<ul><li>Provide high quality proactive application engineering support for both in-house and commercial EDA Mixed-Signal design and verification tools and flows</li><li>Assess, implement and coordinate the development of new capabilities in Mixed-Signal Design and Verification by engaging with EDA vendors</li><li>Work closely with the design teams to understand their requirements and collaborate with device modeling, process development and foundry groups to enable the efficient use of CAD tools and methodologies</li><li>Develop and improve automated QA procedures to improve the efficiency and integrity of AMS CAD flows</li><li>Work closely with the EDA tool vendors to drive new feature additions and resolve tool bugs</li></ul> Experience/Qualification:<ul><li>Bachelor's or Master's degree in Electronics engineering or other relevant technical discipline such as Electrical and Computer Engineering, and a minimum of 4 years of experience</li><li>Proficiency in Cadence SKILL, Python, Perl, Shell-scripting required</li><li>Experience in design and/or layout of Analog and mixed signal circuits is preferred</li><li>Experience in automation of flows using Cadence SKILL is required</li><li>Experience in PDK or physical verification rules development is a plus</li><li>Exposure to deep-submicron manufacturing technologies is a plus</li><li>Strong interpersonal and communication skills are critical for working, influencing and collaborating with product development groups in India and worldwide</li><li>Proficiency in English language</li></ul>]For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export  licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls.  As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.Job Req Type: Experienced          Required Travel: Yes, 10% of the time          Shift Type: 1st Shift/Days<h4>Experience Level</h4>Senior Level

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