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<p>Technologist, ASIC Development Engineering (Physical Design)</p><h4>Company Description</h4><p>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.</p><p>Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.</p><p>Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.</p><h4>Job Description</h4><p><strong>Position Overview:</strong></p><p>We are looking for a highly skilled and experienced individual for SoC PD lead position for driving SoC implementation efforts from RTL to GDSII. This role is pivotal within our talented team of engineers, ensuring that we meet our GDS release timelines, PPA requirements, and all sign-off criteria for our complex semiconductor designs. This role demands a profound technical understanding of the entire implementation cycle, from start to finish, as well as exceptional leadership skills. The successful candidate will work with various functional teams and must possess a strategic vision to drive continuous improvement in our methodologies and processes.</p><p> </p><p><strong>Key Responsibilities:</strong></p><ul><li>To be responsible for leading RTL-to-GDSII SoC implementation effort</li><li>To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc.</li><li>To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity.</li><li>To ensure process compliance during project execution and enable / participate in technical discussions/reviews.</li><li>To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.</li><li>Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow</li><li>Foster a culture of innovation, collaboration, and continuous improvement</li></ul><p>-</p><h4>Qualifications</h4><p>- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field</p><p>- A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs</p><p> </p><ul><li>Proven ability in technically leading a small/medium-sized team for executing projects preferred.</li><li>Hands-on experience on the entire PD Flow from RTL to GDSII</li><li>Should have a good understanding of Floor planning, Power Planning, Placement &amp; Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains.</li><li>Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)</li><li>Exposure to static timing analysis fixes including automated ECO generation.</li><li>Strong in areas on CTS, Power, Bump planning, Floorplan</li><li>Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies.</li><li>Library preparation in any environment (Synopsys, Cadence, etc)</li><li>Working knowledge on Physical verification tasks at lower nodes (database merging/DRC/LVS/ERC/PERC/Antenna/ESD/LUP analysis/fixing) at block level/chip level</li><li>The job would require complete ownership from RTL to GDS for complete SoC</li><li>Exposure to IP Hardening for blocks like SERDES, USB PHY, PCIe, DDR will be an added advantage.</li><li>Working knowledge of scripting languages like Perl and TCL will be considered a plus</li><li>Candidate needs to be self-driven and confident in reporting the status and sharing technical results with customers.</li><li>Must have the ability to present to senior management, work in a geographically dispersed team, and be aware of cross-cultural nuances.</li><li>Should be able to define project milestones, identify risks, and call out mitigation plans.</li></ul><p> </p><h4>Additional Information</h4><p>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.</p><p>Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying</p><h4>Experience Level</h4>Senior Level

SanDisk India Device Design Centre Pvt.Ltd

Electronic Engineer

<p>Principal Engineer, ASIC Development Engineering (IP Verification)</p><h4>Company Description</h4><p>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.</p><p>Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.</p><p>Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.</p><h4>Job Description</h4><p>We are seeking a highly skilled and experienced Principal Engineer to join our ASIC Development Engineering team in Bengaluru, India.</p><p>In this role you will  design and implements IPs and subsystems.</p><p>Dealing the best of class IPs for all SanDisk products</p><ul><li>BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field</li><li>8+ years of experience in ASIC development, with a proven track record of leading complex project</li><li>At  hands on in IP / blocks / subsystem complex design in verilog / sysverilog</li><li>Strong digital design development and execution skills , solving bugs</li><li>Experience in grooming team of 1-4 engineers, interacting with many team</li><li>Deep expirience in debug , solving problem, see the architecture view, proposing solutions.</li><li>Hands-on experience with industry-standard EDA tools and design flows </li><li>Deep knowledge on PCIe,  axi , DMA, AHB interfaces </li><li>Experience in Verification UVM ,  DDR , flash is a plus</li><li>BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field</li><li>Expertise in high-performance and low-power design techniques</li><li>Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly</li></ul><p> </p><h4>Qualifications</h4><ul><li>BE or Master's in Electronics  Engineering,  Electrical Engineering, Computer Engineering, or related field</li><li>10+ years of experience in ASIC development, with a proven track record of leading complex projects</li><li>Advanced knowledge of ASIC design and development, including digital design, verification methodologies, and proficiency in hardware description languages (e.g., Verilog, VHDL)</li><li>Expertise in high-performance and low-power design techniques, with hands-on experience using industry-standard EDA tools</li><li>Strong problem-solving, debugging, and analytical skills to resolve complex technical issues</li><li>Excellent leadership, mentoring, and communication skills, with the ability to guide engineering teams and articulate complex technical concepts</li><li>Understanding of semiconductor industry trends and willingness to work in Bengaluru, India, with occasional travel</li></ul><h4>Additional Information</h4><p>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.</p><p>Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at <a href="mailto:jobs.accommodations@sandisk.com">jobs.accommodations@sandisk.com</a> to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.</p><h4>Experience Level</h4>Senior Level

Chief Engineer

<p>Senior Logic Design Engineer</p><p><span>Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.</span></p><p><span> </span></p><p><span>As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the <strong>Cloud Compute Development Organization (CCDO) </strong>is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. </span></p><p><span> </span><span>We are looking for an <strong>SOC RTL to PD Engineer</strong> to join the team.</span></p><p><span> </span></p><p><span>#azurehwjobs</span><span>   </span></p><h4>Responsibilities</h4><ul><li><span>Ensure high quality deliverables from RTL to Physical Design</span></li><li><span>Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results</span></li><li><span>Create, analyze, and maintain timing constraints/SDCs</span></li><li><span>Analyze and drive UPF solutions for low power checks</span></li><li><span>Drive RTL to Synthesis FEV clean</span></li><li><span>Collaborate with RTL and Physical Design team to address design feedback and drive quality</span></li></ul><h4>Qualifications</h4><ul><li><span>Required Qualifications:</span><ul><li><span>MS with 5+ years of experience or BS with 7+ years of experience. </span></li><li><span>At least 5+ years of experience applying digital design principles in SOC and/or IP development. </span></li><li><span>Strong Static Timing Analysis background; understanding timing signoff fundamentals. </span></li><li><span>Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, and Innovus. </span></li><li><span>Experience with timing constraints management and debug tools supporting constraints quality checks, constraints verification, constraints promotion &amp; demotion. </span></li><li><span>Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints. </span></li><li><span>Understanding in design closure challenges in power and clock domain crossings. </span></li><li><span>Understanding reset and FIFO related design requirements.</span></li></ul></li><li><span>Preferred Qualifications</span><ul><li><span>Experience with FEV and industry standard tools such as Formality and/or Conformal</span></li><li><span>Applied understanding of low power design principles. </span></li><li><span>Highly Proficient in Verilog/System Verilog coding constructs. </span></li><li><span>Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) </span></li><li><span>Strong understanding in clock crossing techniques </span></li><li><span>Strong understanding in IJPF (Low power intent). </span></li><li><span>Ability to write scripts using Perl, TCI, Python etc. </span></li><li><span>Familiarity with Industry standard interface protocols is a plus. </span></li><li><span>Good verbal and written communication skills. </span></li></ul></li></ul><p><span>Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the <a href="https://careers.microsoft.com/us/en/accommodationrequest" rel="noopener" target="_blank">Accommodation request form</a>.</span></p><p> </p><p><span>The ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </span></p><p> </p><p><span>Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.</span></p><h4>Experience Level</h4>Senior Level

Microsoft Corporation India Pvt Ltd.

Embedded Systems Engineer

<p>Staff Engineer, Firmware verification Engineering</p><h4>Company Description</h4><p><strong>Company Description</strong></p><p>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.</p><p>Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.</p><p>Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.</p><p> </p><h4>Job Description</h4><p>Essential Duties and Responsibilities:</p><p>Develop validation strategy including test methodology for assigned firmware modules.<br/>Innovative approach for building the best in class tests packages for validating the firmware.<br/>Analyze, design, program, debug and modify test software and Firmware.<br/>Work often involves special SanDisk tools,<br/>Failure analysis to find the root cause of failure and the solution.<br/>Review testing requirements and influence future SanDisk product design for debug and test.<br/>Interface with stakeholders to ensure firmware verification meets product expectations and needs.<br/>Achieve results in a fast moving, dynamic environment.<br/>Continuously improve the existing processes and systems to keep them up to date with the customer needs and industry trends.</p><p> </p><h4>Qualifications</h4><p>Desired Experience and Skills:</p><p>Qualification:</p><p>• Minimum 6+ years in  Storage or Embedded industry segments <br/>• Experience in Embedded Firmware validation, Test case development, White box testing, Test script development and debugging.<br/>• Experience in programming  (e.g. Assembly, C, C++, Python).<br/>• Experience in doing failure analysis with respect to reproducing and root causing the issues <br/>• Understand Software development Life Cycle.<br/>• Experience working with Flash memory technologies is a plus.<br/>• Knowledge of system architecture is a plus. </p><p>Education: BE/ B.Tech, ME/ M.Tech</p><h4>Additional Information</h4><p>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.</p><p>Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at <a href="mailto:jobs.accommodations@sandisk.com">jobs.accommodations@sandisk.com</a> to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.</p><h4>Experience Level</h4>Senior Level

<p>Sr Manager, Firmware Engineering</p><h4>Company Description</h4><p>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.</p><p>Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.</p><p>Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.</p><p> </p><h4>Job Description</h4><p>In this position, the individual will be responsible for following:</p><ul><li>Designing, implementing, debugging firmware for the next generation storage devices (SD, USB, SATA)</li><li>It includes arriving at algorithms and schemes to cater to the product requirements in alignment with the limitations enforced by the System architecture</li><li>Will be technically driving 10+ member team on feature development and stabilization</li><li>Mentor junior engineers and NCGs</li><li>Provide high level scoping and effort estimates for FW features</li></ul><h4>Qualifications</h4><p> </p><ul><li>Requires BE/BTech degree or equivalent or higher with 12+ years of work experience in FW development field</li><li>Embedded C language experience required</li><li>Must have strong problem-solving skills; experience using logic and protocol analyzers is preferred</li><li>Having experience with FTL and NAND flash or protocols like SD/USB/SATA is highly desirable.</li><li>Ability to achieve results in a fast moving, dynamic environment.</li><li>Self-motivated and self-directed, however, must have demonstrated ability to work well with people.</li><li>Proven desire to work as a team member, both on the same team and outside of the team.</li><li>Ability to work effectively cross-functionally.</li><li>Ability to troubleshoot and analyze complex problems.</li><li>Ability to multi-task and meet deadlines.</li><li>Excellent communication (written and verbal) and interpersonal skills.</li><li>Prior experience of Flash Technology will be an added advantage.</li><li>Deep understanding of Storage Stack/Data path is desirable.</li></ul><h4>Additional Information</h4><p>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.</p><p>Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at <a href="mailto:jobs.accommodations@sandisk.com">jobs.accommodations@sandisk.com</a> to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.</p><h4>Experience Level</h4>Senior Level

Embedded Software Developer

<p>Static Stress Analysis + Isami + Hand calculation</p><p><br></p><p>We're hiring for below position:</p><p><br></p><p><strong>Skills: </strong>Static Stress Analysis + Isami + Hand calculation</p><p><strong>Experience: </strong>6 to 15 years</p><p><strong>Location: </strong>Bangalore</p><p><br></p><p>If interested, share your CV.</p>

Capgemini

Technical Analyst

<p>Functional Validation Professional</p><p><br></p><p>We're hiring below position:</p><p> </p><p><strong>Skills: </strong>Functional Validation </p><p>- Functional Validation activities (NI Test stand, Wireshark, Signalling /Locomotive domain))</p><p><strong>Experience:  </strong>4 to 9 years</p><p><strong>Location: </strong>Bangalore</p><p><br></p><p>If interested, share your CV.</p>

Quality Assurance Associate

<p>Senior Staff SoC Verification Engineer</p><h4>
                
                General Information
            </h4>






                                                Job Title
                                            

                                                                                            Senior Staff SoC Verification Engineer
                                                                                    



                                                Job ID
                                            

                                                                                            12632
                                                                                    



                                                Country
                                            

                                                                                            India
                                                                                    



                                                City
                                            

                                                                                            Bengaluru
                                                                                    



                                                Date Posted
                                            

                                                                                            26-Aug-2025
                                                                                    



                                                Job Category
                                            

                                                                                            Engineering
                                                                                    



                                                Job Subcategory
                                            

                                                                                            SOC Engineering
                                                                                    



                                                Hire Type
                                            

                                                                                            Employee
                                                                                    



                                                Remote Eligible
                                            

                                                                                            No
                                                                                    






<h4>
                
                Descriptions &amp; Requirements
            </h4>






                                                Job Description and Requirements
                                            

<h4 id="isPasted"><b>We Are:</b><p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p><h4><b>You Are:</b></h4><p>You are an experienced SoC Verification professional, passionate about enabling next-generation technologies and delivering robust, high-quality silicon solutions. You thrive in collaborative and fast-paced environments, leveraging your technical expertise and leadership skills to solve complex verification challenges. With a deep understanding of verification methodologies, protocols, and tools, you are adept at translating customer requirements into actionable plans and driving teams to successful outcomes. You embrace change, quickly ramp up on new tools and methodologies, and enjoy mentoring and empowering others to reach their full potential.</p><p>Your approach is inclusive and you value diverse perspectives, recognizing that innovation flourishes in environments where every voice is heard. You are analytical, detail-oriented, and proactive, always anticipating risks and developing strategies to overcome them. You excel at communicating complex technical concepts to both peers and stakeholders, and you are motivated by the opportunity to make a tangible impact on the products shaping tomorrow’s world. As a leader, you are committed to fostering growth within your team and delivering solutions that exceed customer expectations.</p><h4><br/></h4><h4><b>What You’ll Be Doing:</b></h4><ul><li>Engaging directly with Synopsys customers to understand verification needs and define project scope and activities.</li><li>Developing and implementing system design solutions using Synopsys EDA tools and IP.</li><li>Leading a team of engineers in executing pre-silicon verification activities for IPs and subsystems.</li><li>Anticipating technical challenges and risks, and formulating effective resolution and mitigation plans.</li><li>Mentoring and coaching team members to enhance their technical capabilities and performance.</li><li>Reviewing results and reports to provide constructive feedback, driving continuous improvement in quality.</li><li>Reporting project status to management and recommending solutions to address execution issues.</li><li>Collaborating with architects, designers, and verification teams to ensure seamless project execution.</li><li>Contributing to the evolution of verification methodologies and increasing operational efficiency.</li><li>Rapidly learning and deploying new verification tools and methodologies to enable customer success.</li><li>Partnering with other Synopsys teams, including Business Unit Application Engineers and Sales, to broaden and deploy tool and IP solutions.</li></ul><h4><br/></h4><h4><b>The Impact You Will Have:</b></h4><ul><li>Empowering customers to successfully complete their most challenging SoC design and verification projects.</li><li>Enhancing the quality and reliability of advanced silicon chips used in diverse applications.</li><li>Driving innovation in verification methodologies and processes, setting industry standards.</li><li>Mentoring and growing the verification team’s expertise, ensuring readiness for future assignments.</li><li>Improving collaboration and knowledge sharing across multidisciplinary teams.</li><li>Contributing to Synopsys’ reputation as a trusted partner for high-performance computing, automotive, aerospace &amp; defense, and more.</li><li>Accelerating project timelines and improving customer satisfaction through proactive problem-solving.</li><li>Shaping the future of technology by delivering solutions that power smart devices and connected systems worldwide.</li></ul><h4><br/></h4><h4><b>What You’ll Need:</b></h4><ul><li>B.E/B.Tech/M.E/M.Tech in Electronics or related field, with 8+ years’ hands-on experience in SoC/IP/Subsystems verification.</li><li>Strong expertise in pre-silicon verification methodologies (UVM, Coverage Analysis, Verification plan creation, debugging, etc.).</li><li>Proficiency in verification tools such as VCS, waveform analyzers, and integration of third-party VIPs (including Synopsys VIPs).</li><li>Solid understanding of protocols like PCIe, Ethernet, USB, DDR, and processor/interconnect/debug architectures.</li><li>Demonstrated ability to lead and manage verification teams working on complex SoC/IP/Subsystems projects.</li><li>Experience with planning and managing verification activities, including resource estimation and risk management.</li><li>Strong grasp of design concepts, ASIC flows, and stakeholder interactions.</li><li>Excellent communication and interpersonal skills.</li><li>Preferred: Experience with ARM-based technologies (Coresight Debug, Processor architecture, etc.).</li></ul><h4><br/></h4><h4><b>Who You Are:</b></h4><ul><li>Inclusive and collaborative, welcoming diverse perspectives and fostering a positive team culture.</li><li>Proactive problem-solver with strong analytical skills and attention to detail.</li><li>Effective communicator, able to translate complex technical information for varied audiences.</li><li>A natural leader, skilled at mentoring and developing team members.</li><li>Adaptable and eager to learn, staying ahead of industry trends and new technologies.</li><li>Customer-focused, committed to delivering high-quality solutions and exceeding expectations.</li></ul><h4><br/></h4><h4><b>The Team You’ll Be A Part Of:</b></h4><p>You’ll join the System Solutions Group (SSG), a dynamic and diverse team of verification experts, architects, and designers dedicated to delivering tool, methodology, architecture, and design expertise for leading-edge SoC projects. SSG partners with customers from startups to industry leaders across high-performance computing, automotive, aerospace &amp; defense, and more. Together, we collaborate to solve challenging problems, innovate on verification methodologies, and enable the development of world-class silicon solutions.</p><h4><br/></h4><h4><b>Rewards and Benefits:</b></h4><p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p></h4><p><span id="isPasted">At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</span></p><h4>Experience Level</h4>Senior Level

Synopsys India Pvt Ltd

Senior Test Engineer

<p>IVI BSP Display-Touch-Audio Subsystem Engineer</p><h4>At Visteon, the work we do is both relevant and recognized—not just by our organization, but by our peers, by industry-leading brands, and by millions of drivers around the world. That’s YOUR work.</h4><h4>And, as a truly global technology leader in the mobility space, focused on building cross-functional AND cross-cultural teams, we connect you with people who help you grow.</h4><h4>So here, whatever we do is not a job. It’s a mission. As a multi-billion-dollar leader of disruptive change in the industry, we are shaping the future, while enabling a cleaner environment. No other industry offers more fast-paced change and opportunity. We are in the midst of a mobility revolution that will completely change the way we interact with our vehicles, reduce the number of car accidents and fatalities, and make the world a cleaner place. </h4><h4>Visteon is at the epicenter of this mobility revolution.</h4><h4>Two major trends in the automotive industry – the shift to electric vehicles and vehicles with autonomous safety technologies – have created unique opportunities for Visteon. We are the only automotive provider focused exclusively on cockpit electronics – the fastest-growing segment in the industry.</h4><h4>Detailed description: The mission of this role is to design, develop, test and debug BSP software components to build Display-Touch-Audio Subsystem capabilities in In-Vehicle infotainment systems. <br/>How You Will Spend Your Days <br/>• Review requirement specifications and work along with requirements team to resolve issues in the specification and eventually signoff the specification. <br/>• HSIS review and correction along with hardware team. <br/>• Board bring up activities for Display, Touch, Audio subsystem (Serializer-Deserializer, Platform specific frameworks, GMSL/LVDS / FPD Link, DSI/DP, Touch Firmware, Audio calibration and TDM /PCM/DSP) in Linux, Android and QNX systems. <br/>• Interact with hardware teams for board bring up activities, calibration &amp; certification activities and to root cause hardware level issues. <br/>• Interact with cross-functional teams within Visteon and as well as with external teams like chipset vendors to resolve dependencies during development and fixing issues. <br/>• Perform root cause analysis for the issues observed and resolve issues during development, stability and maintenance phase of the project. <br/>• Create documentations for high level design, detailed design and test plans for the software modules. <br/>• Develop and integrate tools/scripts to automate testing. <br/>• Run development testing and document the test reports. <br/>• Create efficient reports with respect to software development, issues resolution and testing. <br/>Technical Knowledge and Skills <br/>• Bachelor’s degree in engineering or related field in Computer Science or Electronics. <br/>• At least 10 to 12 years of experience in developing BSP software components in Linux and Android platforms. <br/>o Good Knowledge of Linux &amp; QNX device drivers as well as peripheral subsystems. <br/>o Strong in C programming skills. <br/>o Working experience in Android AOSP/Linux based infotainment and build environments <br/>o Development experience in Display, Touch, Audio subsystem drivers (Serializer-Deserializer, Platform specific frameworks, GMSL/LVDS FPD Link, DSI, Touch Firmware, Audio calibration and TDM /PCM/DSP configurations, I2S, A2B). <br/>o Experience on DSI, DP port configurations across various SoC platforms like Qualcomm, Samsung, MediaTek. <br/>o Display bridge chip bring-up/configuration experience. <br/>o DRM, Surface flinger, Openwfd, screen related understanding to debug issues. <br/>o TFT panel display timing configuration and debugging. <br/>o Touch controller firmware update, Driver configuration parsing mechanisms. <br/>o Audio driver usage in different chip vendor’s platform; understanding of audio routing; configurations in terms of OS, SoC platform. <br/>o Development experience in serial protocols like I2C, SPI and UART. <br/>o Working experience in QNX hypervisor-based systems <br/>o Good knowledge and working experience on Qualcomm, MediaTek and Samsung SoC platforms. <br/>o Proficient in handling hardware debugging tools like oscilloscope, saleae analyzer, EVK platforms, JTAG debugger <br/>• Creative &amp; strong problem-solving capability resulting in good solution to technical complex software defects <br/>• Strong communication and inter-personal skills</h4><h4><strong>More Good Reasons to Work for Visteon Focusing on the Future</strong></h4><h4>Our company strategy focuses on leading the evolution of automotive digital cockpits and safety solutions. This strategy is driven by constant innovation, and you will support our efforts through your role. We are recognized across the industry for innovation. We have a strong book of business that is expected to drive future growth, along with a customer base that includes almost every automotive manufacturer in the world.</h4><h4><strong>Company Culture</strong></h4><h4>Working at Visteon is a journey in which our employees can develop their strengths and advance their careers while making a difference globally. Join us and help change the world and how we interact with our vehicles. Visteon is where the best technical talent creates the future. Learn more about our culture <a href="https://www.visteon.com/careers/company-culture/" rel="noopener" target="_blank">here.</a></h4><h4> </h4><h4>About Visteon</h4><h4> </h4><h4>Visteon is a global technology company serving the mobility industry, dedicated to creating a more enjoyable, connected and safe driving experience. The company’s platforms leverage proven, scalable hardware and software solutions that enable the digital, electric, and autonomous evolution of our global automotive customers. Visteon products align with key industry trends and include digital instrument clusters, displays, Android-based infotainment systems, domain controllers, advanced driver assistance systems and battery management systems. The company is headquartered in Van Buren Township, Michigan, and has approximately 10,000 employees at more than 40 facilities in 18 countries. Visteon reported sales of approximately $2.8 billion and booked $5.1 billion of new business in 2021.Learn more at <a href="http://www.visteon.com/" rel="noopener" target="_blank">www.visteon.com</a>.</h4><h4>Follow Us</h4><h4>For more information about our company, technologies and products, follow us on <a href="https://www.linkedin.com/company/visteon" rel="noopener" target="_blank">LinkedIn, </a><a href="https://twitter.com/Visteon" rel="noopener" target="_blank">Twitter,</a> <a href="https://www.facebook.com/VisteonCorporation" rel="noopener" target="_blank">Facebook, </a><a href="https://www.youtube.com/user/Visteon" rel="noopener" target="_blank">YouTube </a>and <a href="https://www.slideshare.net/VisteonCorporation" rel="noopener" target="_blank">Instagram. </a>You can also follow our careers-focused channels on <a href="https://twitter.com/VisteonCareers" rel="noopener" target="_blank">Twitter </a>and <a href="https://www.facebook.com/VisteonCareers" rel="noopener" target="_blank">Facebook </a>to keep up with our latest job postings and the great work our employees are doing.</h4><h4>Experience Level</h4>Senior Level

Visteon

<p>SoC Senior Design and Integration Engineer, Google Cloud</p><h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.</li><li>5 years of experience in ASIC/SoC development with Verilog/SystemVerilog.</li><li>Experience in one or more SoC Integration domains and flows (Clocking or debug or fabrics/NoC or Security or low power methodologies).</li><li>Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).<br/></li></ul><br/><h4>Preferred qualifications:</h4><ul><li>Experience with programming languages (e.g., Python, C/C++ or Perl).</li><li>Experience in SoC designs and integration flows.</li><li>Knowledge of bus architectures, fabrics/NoC or memory hierarchies.</li><li>Knowledge of high performance and low power design techniques.</li></ul><h4>About the job</h4>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of  Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. <br/><br/>In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.<h4>Responsibilities</h4><ul><li>Own microarchitecture, implementation and Integration of SoC Chassis and subsystems.</li><li>Perform Quality check flows like Lint, CDC, RDC, VCLP.</li><li>Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Identify and drive Power, Performance and Area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Senior Level

Google India Pvt Ltd

<p>Silicon RTL Design Engineer Networking, Google Cloud</p><h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.</li><li>4 years of experience in ASIC development with Verilog/SystemVerilog, VHDL.</li><li>Experience in micro-architecture and design of IPs and Subsystems.</li><li>Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).</li></ul><br/><h4>Preferred qualifications:</h4><ul><li>Experience in Networking domain like Packet processing, bandwidth management, congestion control etc.</li><li>Experience with scripting languages (e.g., Python or Perl).</li><li>Knowledge of bus architectures, fabrics/NoC, processor design, or memory hierarchies.</li><li>Knowledge of high performance and low power design techniques.<br/><br/></li></ul><h4>About the job</h4><p>In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of  Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.</p><p>In this role, you will develop to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.</p><p>Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.</p><h4>Responsibilities</h4><ul><li>Own microarchitecture and implementation of IPs and subsystems in the Networking domain.</li><li>Work with design team members to close feature definitions and develop microarchitecture specifications. </li><li>Participate in design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.</li><li>Work on Power, Performance and Area improvements for the domains owned.</li></ul><h4>Experience Level</h4>Mid Level

<p>Senior Engineer - Network modeling (Infowork ICM)</p><h4>Company Description</h4><p><strong>Work with Us. Change the World.</strong></p><p>At AECOM, we're delivering a better world. Whether improving your commute, keeping the lights on, providing access to clean water, or transforming skylines, our work helps people and communities thrive. We are the world's trusted infrastructure consulting firm, partnering with clients to solve the world’s most complex challenges and build legacies for future generations.</p><p>There has never been a better time to be at AECOM. With accelerating infrastructure investment worldwide, our services are in great demand. We invite you to bring your bold ideas and big dreams and become part of a global team of over 50,000 planners, designers, engineers, scientists, digital innovators, program and construction managers and other professionals delivering projects that create a positive and tangible impact around the world.</p><p>We're one global team driven by our common purpose to deliver a better world. Join us.</p><h4>Job Description</h4><ul><li>Contribute to engineering design assignments in a team environment on large-scale project teams.</li><li>Candidate should have minimum 5 years working experience on wastewater modelling for ANZ and UK &amp; I region especially on model calibration &amp; verification.</li><li>Candidate should be well versed with Infoworks ICM hydraulic modelling software.</li><li>Having hands on experience with modeling tools like Water GEMS, SewerGEMS, StormCAD, PCSWMM, HEC-RAS, GeoPak would be advantage.</li><li>Capable for leading the project, coordinating with Lead Office, mentoring juniors and ensuring quality checks.</li><li>Complete design activities to specified standards including earthworks modelling and design, sanitary and storm sewer design, watermain design, grading of roads and drive isles, lot grading, and stormwater management design of ponds and other retention systems.</li></ul><h4>Qualifications</h4><ul><li>Master of Engineering degree (or equivalent education) in an appropriate engineering discipline from an accredited college or university. </li><li>Chartered Engineer (CEng), or Professional Engineer (PE) license or equivalent in the relevant field from any global organization (e.g., Institution of Civil Engineers, UK).</li><li>Highly motivated, hardworking, interpersonal, and enthusiastic team player that is willing to learn and adapt to change.</li><li>US/UK/Canada Experience will be added advantage</li><li>Good communication skills, and ability to work well independently at times.</li><li>Able to see the “bigger picture” and take a birds-eye view of projects</li><li>Confident, with the ability to work either independently or as part of a team.</li><li>Ability to work to deadlines and under pressure.</li><li>Accountability for assigned work.</li><li>Accuracy &amp; precision of work.</li><li>Willingness to learn and develop.</li><li>Excellent written and verbal communication skills</li><li>Strong problem-solving skills</li><li>Enthusiastic and Self-motivated.</li><li>Work well within a multidisciplinary team</li></ul><h4>Additional Information</h4><p>AECOM provides a wide array of compensation and benefits programs to meet the diverse needs of our employees and their families. We also provide a robust global well-being program. We’re the world’s trusted global infrastructure firm, and we’re in this together – your growth and success are ours too.<br/><br/>As an Equal Opportunity Employer, we believe in each person’s potential, and we’ll help you reach yours.</p><p>#LI-FS1</p><p><strong>About AECOM</strong> </p><p>AECOM is proud to offer comprehensive benefits to meet the diverse needs of our employees. Depending on your employment status, AECOM benefits may include medical, dental, vision, life, AD&amp;D, disability benefits, paid time off, leaves of absences, voluntary benefits, perks, flexible work options, well-being resources, employee assistance program, business travel insurance, service recognition awards, retirement savings plan, and employee stock purchase plan. </p><p>AECOM is the global infrastructure leader, committed to delivering a better world. As a trusted professional services firm powered by deep technical abilities, we solve our clients’ complex challenges in water, environment, energy, transportation and buildings. Our teams partner with public- and private-sector clients to create innovative, sustainable and resilient solutions throughout the project lifecycle – from advisory, planning, design and engineering to program and construction management. AECOM is a Fortune 500 firm that had revenue of $16.1 billion in fiscal year 2024. Learn more at aecom.com. </p><p><strong>What makes AECOM a great place to work</strong> </p><p>You will be part of a global team that champions your growth and career ambitions. Work on groundbreaking projects - both in your local community and on a global scale - that are transforming our industry and shaping the future. With cutting-edge technology and a network of experts, you’ll have the resources to make a real impact. Our award-winning training and development programs are designed to expand your technical expertise and leadership skills, helping you build the career you’ve always envisioned. Here, you’ll find a welcoming workplace built on respect, collaboration and community - where you have the freedom to grow in a world of opportunity. </p><p>As an Equal Opportunity Employer, we believe in your potential and are here to help you achieve it. All your information will be kept confidential according to EEO guidelines. </p><h4>Experience Level</h4>Senior Level

Aecom India Pvt Ltd

Senior Network Engineer

<p>Silicon Senior Physical Design Engineer, TPU, Google Cloud</p><h4>Minimum qualifications:</h4><ul><li>Bachelor’s degree in Electrical Engineering or equivalent practical experience.</li><li>5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.</li><li>Experience with System on a Chip (SoC) cycles.</li><li>Experience in high-performance, high-frequency, and low-power designs.</li></ul><br/><h4>Preferred qualifications:</h4><ul><li>Master’s degree in Electrical Engineering.</li><li>Experience in coding with System Verilog and scripting with TCL.</li><li>Experience with VLSI design in SoC or multiple-cycles of SoC in ASIC design.</li><li>Experience with layout verification and design rules.</li></ul><h4>About the job</h4>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
<p>In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.</p><p>The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.</p><p>We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.</p>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.<h4>Responsibilities</h4><ul><li>Define and drive the implementation of physical design methodologies.</li><li>Take ownership of one or more physical design partitions or top level.</li><li>Manage timing and power consumption of the design.</li><li>Contribute to design methodology, libraries, and code review. 
</li><li>Define the physical design related rule sets for the functional design engineers.</li></ul><h4>Experience Level</h4>Senior Level

Design Engineer

<p>EIS Engineer</p><p><br></p><p><strong>Role Overview</strong></p><p>We’re looking for a skilled EIS Engineer with a strong background in Medical Device Regulations and Control Systems Design &amp; Development (CSI). This is an exciting opportunity to work on end-to-end product development and ensure compliance with international standards.</p><p><br></p><p><strong> Key Responsibilities</strong></p><ul><li>Lead and contribute to control system design and development for medical devices.</li><li>Ensure compliance with regulatory standards like FDA, ISO 13485, IEC 62304, etc.</li><li>Collaborate with cross-functional teams (hardware, software, QA, RA).</li><li>Prepare and maintain technical documentation for audits and approvals.</li><li>Support risk management, verification &amp; validation, and system integration.</li></ul><p><br></p><p><strong> Requirements</strong></p><ul><li>6–8 years of experience in EIS, medical device development, or control systems engineering.</li><li>Strong understanding of control systems (CSI) methodologies and tools (e.g., MATLAB/Simulink, LabVIEW, PLCs).</li><li>In-depth knowledge of medical device regulations and standards.</li><li>Excellent analytical, documentation, and communication skills.</li><li>BE/BTech or higher in Electronics, Instrumentation, Biomedical, or related fields.</li></ul><p><br></p><p>Share your updated resume now.</p>

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