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Principal SoC Verification Engineer<h4>
 
 General Information
 </h4>






 Job Title
 

 Principal SoC Verification Engineer
 



 Job ID
 

 12631
 



 Country
 

 India
 



 City
 

 Bengaluru
 



 Date Posted
 

 26-Aug-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 SOC Engineering
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

<h4 id="isPasted">We Are:At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.We are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation and SoC Design, we want to meet you.<h4> </h4><h4>You Are:</h4>You are a seasoned engineering professional with 12+ years of hands-on experience in SoC/IP/Subsystems verification, eager to make an impact at the principal level. You thrive in complex technical environments, bringing deep expertise in pre-silicon verification methodologies such as UVM, coverage analysis, and debugging. Your background in electronics engineering is complemented by a robust understanding of ASIC flows, design concepts, and industry protocols including PCIe, Ethernet, USB, and DDR.Leadership comes naturally to you—you guide and mentor teams, fostering growth and excellence, and you’re adept at managing verification activities for large-scale projects. You are a strategic thinker who anticipates challenges and proactively develops risk mitigation plans. Collaboration energizes you, whether working with architects, designers, or cross-functional teams to deliver high-quality solutions. Your communication skills are strong, allowing you to articulate complex technical details clearly to stakeholders and management.You are committed to continuous learning and growth, staying current with new verification tools and Synopsys technologies. Experience with ARM-based technologies, processor architecture, and debug systems further strengthens your profile. Above all, you are passionate about driving innovations in the semiconductor space and excited to help shape the future of smart systems through your expertise and leadership.<h4> </h4><h4>What You’ll Be Doing:</h4><ul><li>Engage with Synopsys customers to understand verification needs and define project scopes and deliverables.</li><li>Lead and mentor a team of engineers to execute pre-silicon verification activities on complex IPs and subsystems.</li><li>Develop verification plans, resource requirements, and risk mitigation strategies to ensure successful project execution.</li><li>Review results and reports, providing continuous feedback to enhance quality and efficiency.</li><li>Report status to management, offering insights and solutions for potential project challenges.</li><li>Collaborate with architects, designers, and pre/post-silicon teams to achieve verification goals.</li><li>Ramp-up on new verification tools and methodologies, leveraging Synopsys Products to enable customer success.</li><li>Work with business unit application engineers and sales teams to develop and deploy tool and IP solutions.</li><li>Drive improvements in verification methodology and execution efficiency across projects.</li><li>Ensure strict adherence to quality standards and best practices in design verification.</li></ul><h4> </h4><h4>The Impact You Will Have:</h4><ul><li>Accelerate customers’ SoC design cycles by delivering high-quality verification solutions.</li><li>Enhance Synopsys’ reputation as a trusted partner in solving complex verification challenges.</li><li>Enable successful product launches for customers in high-performance computing, automotive, aerospace &amp; defense, and more.</li><li>Drive innovation in verification methodologies, contributing to Synopsys’ leadership in EDA tools and IP.</li><li>Mentor and grow the capabilities of the verification team, fostering a culture of excellence and learning.</li><li>Improve project efficiency and execution through effective risk management and proactive problem-solving.</li><li>Strengthen cross-functional collaboration, ensuring seamless integration across design and verification teams.</li><li>Elevate the quality of deliverables, reducing post-silicon issues and increasing customer satisfaction.</li></ul><h4> </h4><h4>What You’ll Need:</h4><ul><li>B.E/B. Tech/M.E/M. Tech in electronics or related field, with a minimum of 12+ years’ experience in SoC/IP/Subsystems verification.</li><li>Expertise in pre-silicon verification: UVM, coverage analysis, verification plan creation, debugging, etc.</li><li>Strong knowledge of industry protocols (PCIe, Ethernet, USB, DDR) and processor/interconnect/debug architectures.</li><li>Hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs).</li><li>Proven ability to lead teams and manage verification activities for complex SoC/IP/Subsystems projects.</li><li>Experience with ARM-based technologies (Coresight Debug, Processor architecture, etc.) is preferred.</li><li>Solid understanding of design concepts, ASIC flows, and stakeholder management.</li></ul><h4> </h4><h4>Who You Are:</h4><ul><li>Inspirational leader with a passion for mentoring and developing engineering talent.</li><li>Excellent communicator, able to articulate technical concepts to diverse audiences.</li><li>Proactive problem solver with strong organizational and analytical skills.</li><li>Collaborative team player, comfortable working in cross-functional and multicultural environments.</li><li>Detail-oriented and quality-focused, committed to delivering best-in-class solutions.</li><li>Adaptable and eager to learn new technologies, tools, and methodologies.</li></ul><h4> </h4><h4>The Team You’ll Be A Part Of:</h4>You’ll join the System Solutions Group (SSG), a dynamic team of experts delivering tool, methodology, architecture, design creation, verification, and physical implementation solutions for leading-edge customers. Our projects span from sub-blocks to full turnkey end-to-end SoCs, supporting startups, industry leaders, commercial entities, and government agencies. The team is dedicated to enabling customers to complete their most challenging SoC design projects in high-performance computing, automotive, aerospace, defense, and beyond.<h4> </h4><h4>Rewards and Benefits:</h4>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</h4>At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

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Bluetooth Testing Engineer Responsibilities:Test Planning and Design:• Develop comprehensive test plans and strategies for Bluetooth and co-existence testing.• Design test cases to assess Bluetooth device performance in the presence of other wireless technologies (e.g., Wi-Fi, LTE, Zigbee).• Identify potential interference sources and scenarios for coexistence testing. Test Execution:• Set up and configure test environments, including hardware and software components.• Execute test cases and record detailed results.• Utilize test equipment such as spectrum analyzers, network analyzers, and Bluetooth protocol analyzers.• Perform automated and manual testing to assess coexistence performance. Analysis and Reporting:• Analyze test results to identify issues related to coexistence and interference.• Collaborate with cross-functional teams to diagnose and resolve coexistence issues.• Document test procedures, results, and findings in detailed reports.• Provide recommendations for improving Bluetooth coexistence performance. Requirements•Bachelor’s or master’s degree in computer science, Electrical Engineering, or a related field.•3 to 6 years of experience in BT Testing or embedded systems.•Strong problem-solving and analytical skills.

Eximietas Design

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Verification EngineerThe Verification Engineer will be responsible for ensuring the quality and reliability of hardware and network systems. They will work closely with the engineering team to develop and execute verification plans, analyze test results, and identify and resolve any issues. The role requires strong problem-solving skills, attention to detail, and the ability to work effectively in a team environment.

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Windchill Architect We are looking for skilled professionals in PTC Windchill for below role: Job Role:&nbsp;Windchill ArchitectExperience: 10 -14 yearsLocation: Hyderabad Immediate joiners are preferred. Interested candidates, please send your resume.

Birlasoft Limited

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Design for Test Engineer Job DescriptionWe are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with a minimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities<ul><li>Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans.</li><li>Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy.</li><li>Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&amp;R IP blocks for Scan, MBIST and other test interfaces.</li><li>Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing.</li><li>Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet.</li><li>Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs.</li><li>Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations.</li><li>Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types.</li><li>Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues.</li><li>Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs.</li><li>Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting.</li><li>Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow.</li><li>Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory.</li><li>Knowledge of LogicBIST with Test point insertion, X-blocking.</li><li>Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements.</li><li>Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug.</li><li>Ability to perform volume diagnostics on the parts to isolate and improve the patterns.</li></ul> Requirements<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design for Test.</li><li>Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows.</li><li>Prior experience working on IP level and SOC level DFT projects.</li><li>Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc.</li><li>Worked in full chip design or complex IP delivery in the area of DFT.</li><li>Experience in post silicon debug, diagnosis and yield enhancements is a plus.</li></ul>

Senior Test Engineer

Consultant - Fatigue & Damage Tolerance Engineer Capgemini is hiring below position:- Designation: ConsultantExperience: 4–6 Years Job Skill: Fatigue &amp; Damage Tolerance EngineerLocation: Bengaluru Note: Please mention the Designation while sharing your CV for reference.To apply, please email your CV.

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Fabrication Quality Engineer

Design Verification Engineer This job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job OverviewWe are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description<ul><li>Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.</li><li>Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM</li><li>Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.</li><li>Analyze and implement System Verilog assertions and coverage (code, toggle, functional).</li><li>Provide mentorship and technical guidance to junior verification engineers.</li><li>Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.</li><li>Ensure verification signoff criteria are met and documentation is comprehensive.</li><li>Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.</li><li>Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.</li><li>Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.</li></ul> Qualifications<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>Master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design Verification.</li><li>Expertise in UVM (Universal Verification Methodology) and System Verilog.</li><li>Prior experience working on IP level and SOC level verification projects.</li><li>Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).</li><li>Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.</li><li>Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.</li><li>Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Proficiency in scripting languages such as shell, Makefile, and Perl.</li><li>Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.</li><li>C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.</li></ul>

Assistant Design Engineer

RTL ENGINEER Experience: 4+ YearsThis job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job Description Required<ul><li>Solid RTL coding experience including</li><li>Microarchitecture of design</li><li>System Verilog and Verilog coding using provided coding styles.</li><li>Understanding of SDC</li><li>Understanding STA reports and how to adjust RTL accordingly.</li><li>Designing for error cases and debug of IP</li><li>Understanding of CDC logic</li><li>Knowledge of lint rules and exceptions</li><li>Design and use of block level simulations to bring up IP.</li><li>Knowledge of AMBA buses and when to use them.</li></ul> Job Description Preferred<ul><li>Experience&nbsp;leading small design team.</li><li>C coding / Firmware skills</li><li>Knowledge on common processor architectures&nbsp;(ARM, RiscV)</li><li>FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA.</li><li>Lab brings up experience, scripting.</li><li>Relevant tool experience such as: Socrates, Core Consultant in addition&nbsp;to standard simulation tools (xcellium, vcs, etc)</li><li>Emulation experience&nbsp;(Zebu, Palladium, etc)</li><li>Board knowledge, component selection, probing, debug.</li><li>JTAG debugging experience (Coresight, Lauterbach, etc).</li><li>Low power design techniques</li></ul> Qualifications<ul><li>E./B.Tech. degree at minimum.</li></ul>

Junior Network Engineer

Windchill Integration Architect We are looking for skilled professionals in PTC Windchill for below role: Job Role:&nbsp;Windchill Integration ArchitectExperience: 9-14 yearsLocation: Hyderabad Immediate joiners are preferred. Interested candidates, please send your resume.

Design Engineer

Linux Kernel Engineer SKILL SET&nbsp;• Linux kernel• Kernel debugging skills• Kernel internals• Device drivers. GOOD TO HAVEDevice Driver / Board Support Packages HW Debugging and Board Bring-up, ARM64 or x86 architecture. Experience - 4-6 YearsShare your updated resume now.

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Engineering - Hardware & Networks Jobs - 1946 Verified Vacancies

Embedded Systems Engineer

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Senior Test Engineer

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