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Silicon Senior Physical Design Engineer, TPU, Google Cloud<h4>Minimum qualifications:</h4><ul><li>Bachelor’s degree in Electrical Engineering or equivalent practical experience.</li><li>5 years of experience with advanced design, including clock/voltage domain crossing, Design for Testing (DFT), and low power designs.</li><li>Experience with System on a Chip (SoC) cycles.</li><li>Experience in high-performance, high-frequency, and low-power designs.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Master’s degree in Electrical Engineering.</li><li>Experience in coding with System Verilog and scripting with TCL.</li><li>Experience with VLSI design in SoC or multiple-cycles of SoC in ASIC design.</li><li>Experience with layout verification and design rules.</li></ul><h4>About the job</h4>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind.The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.<h4>Responsibilities</h4><ul><li>Define and drive the implementation of physical design methodologies.</li><li>Take ownership of one or more physical design partitions or top level.</li><li>Manage timing and power consumption of the design.</li><li>Contribute to design methodology, libraries, and code review. 
</li><li>Define the physical design related rule sets for the functional design engineers.</li></ul><h4>Experience Level</h4>Senior Level

Google India Pvt Ltd

Design Engineer

DV Engineer <ul><li>Experience : 4+ years</li><li>Notice period : immediate to 30 days</li></ul> Share your updated resume now.

ACL Digital

Assistant Design Engineer

Design Verification Engineer <ul><li>Skills - Python, ARM SoCs, Linux, RTOS, System-level development, validation, automation.</li><li>Experience - 3–5 years</li><li>Notice Period: 0–30 Days</li></ul> Send your updated CV to <a rel=\"noopener noreferrer\" href=\"mailto:anushakonda@mirafra.com\" target=\"_blank\">anushakonda@mirafra.com</a>

Mirafra Software Technologies Pvt Ltd

Sr Verification Engineer<h1> </h1>Experience:&nbsp;4-10 YearsAs a Verification Engineer, you will play a crucial role in the development of next-generation Storage Networking ASICs. Your primary responsibilities will include:• Develop a detailed micro-architecture for both module-level and system-level test benchesVerification Micro-Architecture &amp; Documentation:• Produce comprehensive documentation outlining verification strategies and approaches.Firmware and Hardware Co-Simulations:• Conduct co-simulations to ensure seamless integration and functionality between firmware and hardware components.Test Plan Development:• Create detailed test plans, outlining methodologies and criteria for effective verification.Test Bench Coding and Test Writing:• Develop and code test benches, and write tests to validate module-level and system-level functionalities.Debugging:• Troubleshoot and resolve simulation failures at both module and system levels.RTL Code Coverage Analysis and Enhancements:• Analyze RTL code coverage to identify gaps and propose enhancements to improve verification coverage.Scripting for Automation:• Develop scripts to automate various aspects of the verification process, enhancing overall productivity and efficiencyValidation Support:• Assist in FPGA and ASIC validation processes, which includes analyzing Ethernet and PCIe traces and detailed hardware logging during system operation Requirement:• Graduation with 3+ years of hands-on code development experience• A degree in EE, CE, or CS

Modernize Chip Solutions

Testing Engineer

Design Verification Engineer This job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job OverviewWe are seeking an experienced and highly skilled Senior SOC Design Verification Engineer with a minimum of 5 years of hands-on experience in SOC Design Verification. As a key member of our team, you will play a pivotal role in ensuring the robustness and correctness of our cutting-edge System on Chip designs. Job Description<ul><li>Lead and manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.</li><li>Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM</li><li>Conduct Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Collaborate closely with cross-functional teams, architects, designers, and pre/post-silicon verification teams.</li><li>Analyze and implement System Verilog assertions and coverage (code, toggle, functional).</li><li>Provide mentorship and technical guidance to junior verification engineers.</li><li>Manage and lead a dynamic team of verification engineers, fostering a collaborative and innovative work environment.</li><li>Ensure verification signoff criteria are met and documentation is comprehensive.</li><li>Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.</li><li>Adhere to quality standards, implement good test practices, and contribute to the continuous improvement of verification methodologies.</li><li>Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.</li></ul> Qualifications<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>Master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR</li><li>PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design Verification.</li><li>Expertise in UVM (Universal Verification Methodology) and System Verilog.</li><li>Prior experience working on IP level and SOC level verification projects.</li><li>Proficient in verification tools such as VCS, Xsim, waveform analyzers, and third-party VIP integration (e.g., Synopsys VIPs and Cadence VIPs).</li><li>Hands-on experience with UFS (Universal Flash Storage), Ethernet, PCIe, CXL, MIPI protocols.</li><li>Solid understanding of low-speed peripherals (I2C/I3C, SPI, UART, GPIO, QSPI) and high-speed protocols.</li><li>Experience in DDR, HBM, Gate-level simulations, and power-aware verification using Xprop and UPF.</li><li>Proficiency in scripting languages such as shell, Makefile, and Perl.</li><li>Strong understanding of processor-based SOC verification, including native, Verilog, System Verilog, and UVM mixed environment.</li><li>C-System Verilog handshake and writing C test cases for bootup verification. Excellent problem-solving, analytical, and debugging skills.</li></ul>

Eximietas Design

RTL ENGINEER Experience: 4+ YearsThis job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job Description Required<ul><li>Solid RTL coding experience including</li><li>Microarchitecture of design</li><li>System Verilog and Verilog coding using provided coding styles.</li><li>Understanding of SDC</li><li>Understanding STA reports and how to adjust RTL accordingly.</li><li>Designing for error cases and debug of IP</li><li>Understanding of CDC logic</li><li>Knowledge of lint rules and exceptions</li><li>Design and use of block level simulations to bring up IP.</li><li>Knowledge of AMBA buses and when to use them.</li></ul> Job Description Preferred<ul><li>Experience&nbsp;leading small design team.</li><li>C coding / Firmware skills</li><li>Knowledge on common processor architectures&nbsp;(ARM, RiscV)</li><li>FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA.</li><li>Lab brings up experience, scripting.</li><li>Relevant tool experience such as: Socrates, Core Consultant in addition&nbsp;to standard simulation tools (xcellium, vcs, etc)</li><li>Emulation experience&nbsp;(Zebu, Palladium, etc)</li><li>Board knowledge, component selection, probing, debug.</li><li>JTAG debugging experience (Coresight, Lauterbach, etc).</li><li>Low power design techniques</li></ul> Qualifications<ul><li>E./B.Tech. degree at minimum.</li></ul>

Junior Network Engineer

Design for Test Engineer Job DescriptionWe are seeking an experienced and highly skilled Senior SOC Design for Test Engineer with a minimum of 5 years of hands-on experience in SOC Design for Test. As a key member of our team, you will play a pivotal role in ensuring the testability, manufacturability, and quality of our cutting-edge System on Chip designs Key Responsibilities<ul><li>Lead and manage SOC Design for Test efforts for complex projects, ensuring the successful execution coverage, manufacturability, and quality plans.</li><li>Develop full chip and block level DFT implementation from the DFx Specifications and product coverage, quality, and manufacturability goals. Define and implement Test controllers at top level and block level, fuse controllers, test clocking strategy, chip I/O test strategy and HSIO test strategy.</li><li>Define JTAG TAP, boundary scan, I/O Test JTAG access, IEEE1687 iJTAG network and instrument design and implementation. Define the Test Interface for each of the P&amp;R IP blocks for Scan, MBIST and other test interfaces.</li><li>Define hierarchical block isolation, Test clocking and On Chip Clock controllers and reset methodology. Define scan and MBIST timing at the top level and block level timing.</li><li>Analyse block level RTL or gates to ensure that scalability and coverage is satisfied as per the design goals. Ensure that DFT is provided to fix the DFT violations to ensure that the design goals are meet.</li><li>Analyse compression requirements for each of the blocks, define Intest and Extest compression requirements and define the requirements for compression engines. Synthesize compression engines for each of the blocks. Create the collaterals for compression for the IPs.</li><li>Block level scan insertion as well as development of the scan wrappers for the blocks. Do scan insertion on the blocks, analyse scan DRC, implement DFT fixes. Create scan protocol files for designs, create scan inserted netlist, create scan definitions as well as scan definition files for PD. Perform ATPG on the scan inserted netlist, analyse DRC and coverage violations.</li><li>Deep knowledge of different scan models Stuck-at, transition test, path-delay, bridging, cell aware, small-delay transition, IDDQ test etc. Ability to analyse coverage for each of the model types.</li><li>Running GLS with or without timing for the scan vectors. Ability to debug the failures and working with timing and PD teams to fix the timing issues.</li><li>Understanding of pattern delivery to the post-silicon test engineering teams. Delivering to the Test engineering the Test pin muxing and other full chip requirements for the Test Engineering Team. Understanding tester requirements and delivering the patterns in the formats that the tester teams needs.</li><li>Implement pattern retargeting. Create grey box models for blocks. Coverage analysis of full chip consolidating Intest and Extest patterns. Knowledge of Top level scan architecture and creating flow to create pattern retargeting.</li><li>Knowledge of Streaming Scan Network and other Top level scan pin sharing and implementing the block to top level pattern generation for this flow.</li><li>Implementing Memory Testing and MBIST. Knowledge of Memory defect models and test algorithms. Knowledge of memory bit mapping and redundancy analysis. Implementing memory repair and fuse sharing among various memory.</li><li>Knowledge of LogicBIST with Test point insertion, X-blocking.</li><li>Full chip DFT delivery for tapeout including but not limited to DFT netlist verification, pattern delivery, Tester requirements.</li><li>Debug DFT patterns post silicon, ability to analyse chain test patterns for failures, scan pattern failures. Analyse MBIST pattern failures, yield and repair debug.</li><li>Ability to perform volume diagnostics on the parts to isolate and improve the patterns.</li></ul> Requirements<ul><li>Bachelor’s degree in computer science, Electrical/Electronics Engineering, or related field. OR master’s degree in computer science, Electrical/Electronics Engineering, or related field. OR PhD in Computer Science, Electrical/Electronics Engineering, or related field.</li><li>5+ years of hands-on experience in SOC Design for Test.</li><li>Expertise in DFT tools and flows in scan intertion, ATPG, GLS simulation, diagnosis flows.</li><li>Prior experience working on IP level and SOC level DFT projects.</li><li>Proficient in DFT tools from Siemens (Tessent), Synopsys DFTmax, Tetramax, Spyglass DFT advisor, Genius DFT, Modus, VCS, Xcelium etc.</li><li>Worked in full chip design or complex IP delivery in the area of DFT.</li><li>Experience in post silicon debug, diagnosis and yield enhancements is a plus.</li></ul>

Senior Test Engineer

Consultant - Fatigue & Damage Tolerance Engineer Capgemini is hiring below position:- Designation: Consultant Experience: 4–6 Years Job Skill: Fatigue &amp; Damage Tolerance Engineer Location: Bengaluru Note: Please mention the Designation while sharing your CV for reference.To apply, please email your CV.

Capgemini

Fabrication Quality Engineer

EIS Engineer Role OverviewWe’re looking for a skilled EIS Engineer with a strong background in Medical Device Regulations and Control Systems Design &amp; Development (CSI). This is an exciting opportunity to work on end-to-end product development and ensure compliance with international standards. Key Responsibilities<ul><li>Lead and contribute to control system design and development for medical devices.</li><li>Ensure compliance with regulatory standards like FDA, ISO 13485, IEC 62304, etc.</li><li>Collaborate with cross-functional teams (hardware, software, QA, RA).</li><li>Prepare and maintain technical documentation for audits and approvals.</li><li>Support risk management, verification &amp; validation, and system integration.</li></ul> Requirements<ul><li>6–8 years of experience in EIS, medical device development, or control systems engineering.</li><li>Strong understanding of control systems (CSI) methodologies and tools (e.g., MATLAB/Simulink, LabVIEW, PLCs).</li><li>In-depth knowledge of medical device regulations and standards.</li><li>Excellent analytical, documentation, and communication skills.</li><li>BE/BTech or higher in Electronics, Instrumentation, Biomedical, or related fields.</li></ul> Share your updated resume now.

Teamware Solutions

Technical Operations Associate

LDD Developer We're hiring below position: Position: LDD DeveloperExperience: 6+ yearsLocation: Bangalore If you're interested, please share your profile.

Developer

WLAN Test Engineer Experience: 4+ YearsThis job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job OverviewAs a WLAN Test Engineer, your primary responsibility is to assess the functionality and performance of wireless networks/Devices. This includes conducting various tests to verify the network's speed, coverage, security, and overall reliability. You'll collaborate with Developers and quality assurance teams to identify and resolve any issues that may arise during testing. Additionally, you may be involved in designing test plans, executing test cases, analysing test results. Job Description<ul><li>Develop and execute test plans and test cases to assess WLAN performance, reliability, and security.</li><li>Conduct manual and automated tests to validate network configurations, protocols, and features.</li><li>Perform regression testing to ensure that new changes or updates do not adversely affect network functionality.</li><li>Identify, isolate, and document defects or issues found during testing, and work closely with development teams to resolve them.</li><li>Collaborate with cross-functional teams to understand product requirements and provide input on design and implementation considerations.</li><li>Utilize testing tools and equipment to simulate real-world network scenarios and assess performance under different conditions.</li><li>Analyze test results and provide detailed reports to stakeholders, including recommendations for network optimization and improvement.</li><li>Stay updated on industry trends, best practices, and emerging technologies related to WLAN</li><li>testing and network management.</li></ul> Qualifications<ul><li>Bachelor’s degree in Computer Science, Information Technology, Electrical Engineering, or a related field.</li><li>Proven experience in WLAN testing, network testing, or a similar role.</li><li>Proficiency in network protocols such as TCP/IP, UDP, DHCP, DNS, and HTTP.</li><li>Strong understanding of wireless networking technologies, including Wi-Fi standards (802.11a/b/g/n/ac/ax), RF fundamentals, and WLAN security protocols (WPA, WPA2, WPA3).</li><li>Familiarity with network testing tools and equipment such as traffic generators, protocol analyzers, spectrum analyzers, and wireless sniffers.</li><li>Experience with Android tools and devices is preferred.</li><li>Excellent analytical and problem-solving skills, with the ability to troubleshoot complex network issues.</li><li>Effective communication skills, with the ability to collaborate with cross-functional teams and communicate technical concepts to non-technical stakeholders.</li><li>Detail-oriented approach with a commitment to producing high-quality work and delivering accurate test results.</li></ul>

Associate Network Engineer

Senior Analog Layout Engineer Experience - 4-6 years Please share your CV at <a rel=\"noopener noreferrer\" href=\"mailto:prasad.adakambarribabu@moschip.com\" target=\"_blank\">prasad.adakambarribabu@moschip.com</a>

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