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Bluetooth Testing Engineer Responsibilities:Test Planning and Design:• Develop comprehensive test plans and strategies for Bluetooth and co-existence testing.• Design test cases to assess Bluetooth device performance in the presence of other wireless technologies (e.g., Wi-Fi, LTE, Zigbee).• Identify potential interference sources and scenarios for coexistence testing. Test Execution:• Set up and configure test environments, including hardware and software components.• Execute test cases and record detailed results.• Utilize test equipment such as spectrum analyzers, network analyzers, and Bluetooth protocol analyzers.• Perform automated and manual testing to assess coexistence performance. Analysis and Reporting:• Analyze test results to identify issues related to coexistence and interference.• Collaborate with cross-functional teams to diagnose and resolve coexistence issues.• Document test procedures, results, and findings in detailed reports.• Provide recommendations for improving Bluetooth coexistence performance. Requirements•Bachelor’s or master’s degree in computer science, Electrical Engineering, or a related field.•3 to 6 years of experience in BT Testing or embedded systems.•Strong problem-solving and analytical skills.

Eximietas Design

Test Engineer

RTL ENGINEER Experience: 4+ YearsThis job might be for you if<ul><li>You enjoy solving problems. You love taking on difficult challenges and finding creative solutions.</li><li>You don’t know the answer but will dig until you find it.</li><li>You communicate clearly. You write well.</li><li>You are motivated and driven. You volunteer for new challenges without waiting to be asked. You will take ownership of the time you spend with us and make a difference.</li><li>You can impress our customers with your enthusiasm to solve their issues (and solve them!)</li></ul> Job Description Required<ul><li>Solid RTL coding experience including</li><li>Microarchitecture of design</li><li>System Verilog and Verilog coding using provided coding styles.</li><li>Understanding of SDC</li><li>Understanding STA reports and how to adjust RTL accordingly.</li><li>Designing for error cases and debug of IP</li><li>Understanding of CDC logic</li><li>Knowledge of lint rules and exceptions</li><li>Design and use of block level simulations to bring up IP.</li><li>Knowledge of AMBA buses and when to use them.</li></ul> Job Description Preferred<ul><li>Experience&nbsp;leading small design team.</li><li>C coding / Firmware skills</li><li>Knowledge on common processor architectures&nbsp;(ARM, RiscV)</li><li>FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA.</li><li>Lab brings up experience, scripting.</li><li>Relevant tool experience such as: Socrates, Core Consultant in addition&nbsp;to standard simulation tools (xcellium, vcs, etc)</li><li>Emulation experience&nbsp;(Zebu, Palladium, etc)</li><li>Board knowledge, component selection, probing, debug.</li><li>JTAG debugging experience (Coresight, Lauterbach, etc).</li><li>Low power design techniques</li></ul> Qualifications<ul><li>E./B.Tech. degree at minimum.</li></ul>

Junior Network Engineer

Senior Analog Layout Engineer Experience - 4-6 years Please share your CV at <a rel=\"noopener noreferrer\" href=\"mailto:prasad.adakambarribabu@moschip.com\" target=\"_blank\">prasad.adakambarribabu@moschip.com</a>

MosChip Technology Ltd

Electronic Engineer

GPIO Circuit Design Engineering ManagerTitle: GPIO Circuit Design Engineering ManagerAbout GlobalFoundriesGlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.Job Summary:The GPIO Manager will lead the design, development, and delivery of GPIO IP blocks and related IO subsystems for advanced semiconductor products. This role involves cross-functional collaboration with architecture, design, verification, physical design, and product engineering teams to ensure high-quality, robust, and scalable IO solutions.Key Responsibilities:<ul><li>Define GPIO architecture and specifications in collaboration with system architects.</li><li>Lead a team of design and verification engineers to deliver GPIO IP blocks.</li><li>Manage project schedules, deliverables, and resource allocation.</li><li>Ensure compliance with industry standards (e.g., JEDEC, IEEE) and internal quality metrics.</li><li>Interface with SoC integration teams to support GPIO integration and debug.</li><li>Drive innovation in IO design for power, performance, and area optimization.</li><li>Collaborate with EDA vendors and internal CAD teams for tool flows and methodology improvements.</li><li>Support silicon bring-up and validation of GPIO functionality.</li><li>Provide technical leadership and mentorship to junior engineers.</li></ul>Required Skills &amp; Qualifications:<ul><li>Bachelor's or Master's degree in Electrical Engineering, Electronics, or related field.</li><li>15+ years of experience in semiconductor IP design, with at least 3 years in a leadership role.</li><li>Deep understanding of digital and mixed-signal IO design principles.</li><li>Knowledge of process technology impact on circuit design is  a plus</li><li>High Speed I/O Design is also plus.</li><li>Experience with RTL design (Verilog/VHDL), synthesis, and timing closure.</li><li>Familiarity with ESD, pad ring design, and physical verification flows.</li><li>Strong project management and communication skills.</li><li>Experience with silicon validation and lab debug tools is a plus.</li></ul>Preferred Qualifications:<ul><li>Prior experience managing GPIO or similar IO IP blocks.</li><li>Knowledge of low-power design techniques and IO reliability.</li></ul>GlobalFoundries is an equal opportunity employer, cultivating a diverse and inclusive workforce. We believe having a multicultural workplace enhances productivity, efficiency, and innovation whilst our employees feel truly respected, valued and heard.  As an affirmative employer, all qualified applicants are considered for employment regardless of age, ethnicity, marital status, citizenship, race, religion, political affiliation, gender, sexual orientation and medical and/or physical abilities. All offers of employment with GlobalFoundries are conditioned upon the successful completion of background checks, medical screenings as applicable and subject to the respective local laws and regulations. Information about our benefits you can find here: <a href="https://gf.com/about-us/careers/opportunities-asia" rel="noopener noreferrer" target="_blank">https://gf.com/about-us/careers/opportunities-asia</a> <h4>Experience Level</h4>Senior Level

Globalfoundries Engineering Private Limited

Electrical Design Engineer

Senior Embedded Software Engineer Key Skills Required:<ul><li>Strong in Python Coding (9/10)</li><li>Wi-Fi (802.11 a/b/g/n/ac/ax) or Openthread (8/10)</li><li>Linux &amp; Git basics (8/10)</li></ul> Good-to-have: Matter protocol** (6–7/10)Experience: 5+ Years Share your updated resume now.

Votary Softech Solutions Pvt Ltd

Embedded Software Developer

Associate Electronics RF Design and Analysis EngineerAssociate Electronics RF Design and Analysis EngineerCompany:Boeing India Private LimitedOverview As a leading global aerospace company, Boeing develops, manufactures and services commercial airplanes, defense products and space systems for customers in more than 150 countries. As a top U.S. exporter, the company leverages the talents of a global supplier base to advance economic opportunity, sustainability and community impact. Boeing’s team is committed to innovating for the future, leading with sustainability, and cultivating a culture based on the company’s core values of safety, quality and integrity. Technology for today and tomorrowThe Boeing India Engineering &amp; Technology Center (BIETC) is a 5500+ engineering workforce that contributes to global aerospace growth. Our engineers deliver cutting-edge R&amp;D, innovation, and high-quality engineering work in global markets, and leverage new-age technologies such as AI/ML, IIoT, Cloud, Model-Based Engineering, and Additive Manufacturing, shaping the future of aerospace. People-driven cultureAt Boeing, we believe creativity and innovation thrives when every employee is trusted, empowered, and has the flexibility to choose, grow, learn, and explore. We offer variable arrangements depending upon business and customer needs, and professional pursuits that offer greater flexibility in the way our people work. We also believe that collaboration, frequent team engagements, and face-to-face meetings bring together different perspectives and thoughts – enabling every voice to be heard and every perspective to be respected.  No matter where or how our teammates work, we are committed to positively shaping people’s careers and being thoughtful about employee wellbeing.With us, you can create and contribute to what matters most in your career, community, country, and world. Join us in powering the progress of global aerospace. Position Overview Boeing India Engineering has an immediate opening for an Associate Electronics RF Design and Analysis Engineer to work in areas of RF design. This position offers a unique opportunity to work complex technical challenges in support of safety operation and return to service. This role will be based out of Bangalore, India. Position Responsibilities:<ul><li>Responsible for RF and mixed signal designs.</li><li>Design and simulate RF circuits for cellular modules including LNAs, filters, Diplexers, switching and matching networks.</li><li>Perform testing and validation of RF components and systems - RF amplifiers, filters, and antennas - to validate performance against specifications.</li><li>Perform RF validation, tuning, and debugging using tools such as VNA, spectrum analyzers, and signal generators</li><li>Perform simulation of filters and antenna synthesis using tools like Ansys HFSS</li><li>Perform circuit design, requirements and interface definition and design verification.</li><li>Design to meet EMI/EMC, safety and environmental compliance.</li><li>Develop and optimize RF systems supporting Wifi,4G LTE and 5G.</li><li>Execute testing of designs in Labs for functional, performance and stress environments apart from system integration  </li></ul>Basic Qualifications (Required Skills and Experience)<ul><li>Bachelor’s or Master’s Degree is required as a basic qualification in Electronics and Communication Engineering with 4 to 8 years of relevant experience. </li></ul>Preferred Qualifications (Desired Skills/Experience):<ul><li>Candidate should have experience in RF Design integration capabilities for Wireless communications and 5G integration</li><li>Candidate should have strong experience in high-speed design clocking, Ethernet/Serdes/MIPI designs</li><li>Candidate should have strong experience in knowledge of using simulation tools like SABER RD and creating simulation models with MATLAB and SABER</li><li>Candidate should have experience with Power Integrity analysis, Hyperlynx SI and Mentor suite of eCAD tools</li><li>Candidate should have basic knowledge of cellular and Wi-Fi standards</li></ul>Relocation:<ul><li>This position does offer relocation within INDIA.</li></ul>Language Requirements:Not ApplicableEducation:Bachelor's Degree or EquivalentRelocation:This position offers relocation based on candidate eligibility.Security Clearance:This position does not require a Security Clearance.Visa Sponsorship:Employer will not sponsor applicants for employment visa status.Contingent Upon Award ProgramThis position is not contingent upon program awardShift:Not a Shift Worker (India)<h4>Experience Level</h4>Mid Level

Boeing India Pvt Ltd

MBD + M-Scripting Engineer We’re Hiring: MBD + M-Scripting EngineerNotice period: Immediate to max 30 daysExperience: 3 – 6 Years We’re looking for MBD + M-Scripting Engineers with experience in any of the following:<ul><li>Design and development of interactive tools using MATLAB App Designer</li><li>Translating functional requirements into structured MATLAB applications and test cases</li><li>Integration of dynamic tables, charts, and plots into MATLAB GUIs</li><li>Regression testing across software releases</li><li>Workflow optimization and automation for performance enhancement</li><li>Hands-on experience in MATLAB development and M-scripting</li><li>Working knowledge of Python and/or C/C++</li><li>Strong problem-solving and debugging skills</li></ul> If interested, share your updated CV.

Capgemini

Design Engineer

L2/L3 Developers We are looking for L2/L3 Developers.Experience Level:&nbsp;4+ years Job Description:<ul><li>Strong in C programming</li><li>L2/L3/NMS – Any 2 protocol knowledge: DHCP, SNMP, AAA, ACL, TLS/SSL, NTP, LAG, STP,</li><li>RSTP, MSTP, RSTP, Multi-chassis LAG, OSPF, BGP</li><li>Strong in GDB debugging</li><li>Strong analytical and problem-solving skills</li><li>Strong in Data structures, Algorithms</li></ul> Any one of the following skill<ul><li>System: LINUX with Networking knowledge, I2C, driver, MAC and PHY, Knowledge on Marvel and Broadcom chipsets.</li><li>Very good in verbal and written communication</li></ul>

Haddows Infotech

Software Engineer III

DFT Design Engineer -Memory Team As one of the largest R&amp;D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products.&nbsp; Roles and Responsibilities<ul><li>Good Experience in Top/Block, FLAT/Hier DFT insertion flow methodologies</li><li>Executed scan &amp; MBIST insertion, ATPG and verification at full chip level</li><li>Experience in timing closure in DFT modes - understanding of shift, capture timing constraints, MBIST constraints and their impacts</li><li>Generate, review and validate DFT constraints to achieve timing closure of high speed design</li><li>Experience in timing closure in DFT modes, RTL analysis, logic synthesis, physical design, signoff verification (STA, Formality, Simulations)&nbsp;</li><li>Exposure to analog and mixed signal IP tests such as PLLs, MIPI etc., methods of their pattern generation and verification</li><li>Exposure to post-silicon bring-up. Diagnosis and debug methods to arrive at fail points for logic or memory tests</li><li>Should be able to comprehend architecture and associated limitations with respect to DFT and be able to predict the schedule, amount of task and personnel involved</li><li>Understanding of Power Estimation/Management for DFT modes is preferred</li><li>Mentor juniors, support periodic training sessions, work with teams across sites and cross-functional teams and lead by examples</li><li>Strong written and oral communication skills</li></ul> Experience – 5+ Years Qualifications<ul><li>B.Tech/B.E/M.Tech/M.E</li></ul>

Samsung India Electronics Pvt Ltd 

Audio Driver Developer We're hiring below position: Position: Audio Driver DeveloperExperience: 8+ yearsLocation: Bangalore If you're interested, please share your profile.

C Embedded Developer Capgemini is hiring C Embedded Developer. Job Requirement:- *Experience*: Minimum 2 to 4 years or 4 to 6 years in C embedded development.- *Location*: Noida.- *Interview*: Face-to-face interviews.- *Joining*: Immediate joiners required. How to Apply: Share your CV.

Senior System Power and Performance Architect, Silicon<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.</li><li>8 years of experience with computer architecture, performance and power analysis.</li><li>Experience with Camera and GenAI workloads and dataflows.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.</li><li>Experience with use case datapaths, IP-level and SoC-level performance KPIs and power management concepts.</li><li>Experience with Post-Signal Integrity (SI) power productization work.</li><li>Experience of software and architectural design decisions on system performance, power and thermal behavior.</li></ul><h4>About the job</h4>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.<h4>Responsibilities</h4><ul><li>Architect and drive end-to-end low power solutions for Google Tensor mobile SoCs to optimize Power-Performance-Area (PPA) under battery life and thermal constraints. Special focus on camera and GenAI use cases, and other mobile apps developed by Google such as Chrome.</li><li>Create use case workload and data and control flow models for use case power, performance, thermal and DoU (days-of-use) evaluation to drive Hardware (HW) and Software (SW) architecture definitions.</li><li>Write code to develop simulators and models to evaluate mobile use cases.</li><li>Define power/performance KPIs, set SoC/IP-level power/performance targets, guide cross-functional teams to achieve these targets, perform use case level power roll-ups and track KPIs through the design cycle.</li><li>Drive power-performance what-if trade-off analysis to guide product roadmap and feature decisions.</li></ul><h4>Experience Level</h4>Senior Level

Google India Pvt Ltd

Senior System Engineer

GPU Design Verification Engineer<h4>Minimum qualifications:</h4><ul><li>Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering or equivalent practical experience.</li><li>3 years of experience with standard GPU workloads like Manhattan/3DMark.</li><li>Experience with GPU architecture and AMBA Bus protocols like AHB/AXI/ACE.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.</li><li>Experience with performance verification of ASICs and Application-Specific Integrated Circuit (ASIC) components.</li><li>Experience with verification of low power techniques.</li></ul><h4>About the job</h4>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.<h4>Responsibilities</h4><ul><li>Be part of a team to verify digital design blocks (e.g., CPU, Graphics Processing Unit (GPU), Image processor) by understanding the design specification and interacting with design engineers to identify important verification scenarios.</li><li>Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.</li><li>Identify and write all types of coverage measures for stimulus and corner-cases.</li><li>Debug tests with design engineers to deliver functionally correct design blocks.</li><li>Close coverage measures to identify verification holes and to show progress towards tape-out.</li></ul><h4>Experience Level</h4>Mid Level

Testing Engineer

MIL-SIL Engineer We’re Hiring: MIL-SIL Engineer Notice period: Immediate to max 30 daysExperience: 3 – 6 Years We’re looking for MIL-SIL Engineers with experience in any of the following:<ul><li>Unit verification of AUTOSAR-based Simulink/TargetLink models</li><li>Requirement analysis and test specification creation</li><li>Code coverage, model quality, and validation (MIL, SIL)</li><li>Model-based testing using Synopsys TPT</li><li>Auto-code generation using MATLAB, Simulink, Stateflow, TargetLink</li><li>AUTOSAR architecture and model development</li><li>Scripting knowledge in MATLAB / Python</li><li>Configuration management tools: PVCS, SVN, GIT</li><li>Requirement management tools: PREEVision / DNG</li></ul> Mandatory Skills:<ul><li>MIL-SIL, Python / M-Scripting, TPT, MATLAB, Simulink, Stateflow, TargetLink</li></ul> If interested, share your updated CV.

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Engineering - Hardware & Networks Jobs - 1686 Verified Vacancies

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