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Principal - ASIC Digital Design (Physical Implementation/Design/STA)<h4>
 
 General Information
 </h4>






 Job Title
 

 Principal - ASIC Digital Design (Physical Implementation/Design/STA)
 



 Job ID
 

 6673
 



 Country
 

 India
 



 City
 

 Noida
 



 Date Posted
 

 28-Sep-2024
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 ASIC Digital Design
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

Principal - ASIC Digital Design (Physical Implementation/Design/STA, experience - 12+ Years) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What You’ll Be Doing: * Working on new processes for physical implementation flows and cutting-edge technology nodes. * Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. * Defining signoff criteria with a strong focus on Timing Closure. * Maturing the physical implementation guide used for customers and internal hardening teams. * Participating in next-generation physical design methodology and flow development. * Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. * Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints. The Impact You Will Have: * Ensuring the optimization and successful implementation of cutting-edge technology nodes. * Contributing to the development of high-performance silicon chips and software content. * Enhancing the efficiency and performance of Synopsys’ IPs through rigorous timing closure and signoff criteria. * Improving customer satisfaction by maturing physical implementation guides. * Supporting the achievement of Synopsys' operational goals through innovative design solutions. What You’ll Need: * Extensive experience with ASIC design flow and hierarchical physical design strategies. * Strong background in timing analysis, constraints management, and frontend synthesis. * Experience with physical-aware synthesis, formality, and various verification strategies. * Knowledge of Primepower-based power analysis and clock gating for power reduction. * Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. * Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team You’ll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Synopsys India Pvt Ltd

Mechanical CAD Designer

System Testing & Commissioning Engineer We are Hiring at <a rel="noopener noreferrer" href="\&quot;https://www.linkedin.com/company/l&amp;t-technology-services-limited/\&quot;" target="_blank">L&amp;T Technology Services</a>. Role - System Testing &amp; Commissioning EngineerNotice - Immediate -30 DaysThe ideal candidate should have experience in Metro rail telecom Systems like CCTV, Master clock, Telephone, Fots, System Engineering / T&amp;C. Description<ul><li>Telecommunication systems testing and commissioning FOTS CCTV Clock Radio Telephone systems and Cyber security Etc.</li><li>Identification and management of technical risks in accordance with the Project management process.</li><li>Lead system design of respective system assigned, as per approved design plan</li><li>Define the overall subsystem design including BOQ, system performance parameters, test plans, of the sub-system. System design inputs, requirements finalization.</li></ul> Experience<ul><li>5 years in similar work experience is mandatory</li><li>B-Tech ECE/EEE</li><li>Experience 7-10 Years</li></ul>

L&T Technology Services Ltd

Test Engineer

System Engineer <ul><li>Notice period: Immediate joiners up to 60 days</li><li>Experience : 10+years</li></ul> Share your updated cv to <a rel=\"noopener noreferrer\" href=\"mailto:neetika_yadav@onwardgroup.com\" target=\"_blank\">neetika_yadav@onwardgroup.com</a>

Onward Technologies Limited

System Engineer

FPGA Engineer Hiring for FPGA Engineer who is having good exposure in Ethernet.<ul><li>Experience- 8 to 12&nbsp;years</li><li>Immediate to 30 days joiners</li></ul> Share your updated resume now.

Sasken Technologies Ltd

Embedded Systems Engineer

Comos Software + P&ID+ Electrical/Mechanical Professional We're hiring below position: Skills: Comos Software + P&amp;ID+ Electrical/Mechanical ProfessionalExperience:5 to 8 years If interested, share your CV.

Capgemini

Mechanical Service Engineer

Infrastructure Engineering IIIYour role will be instrumental in shaping the future at one of the world's largest and most influential companies.As a member of our Infrastructure Platforms Engineering team, you will  join a high-performing team dedicated to developing and deploying large-scale infrastructure solutions that support JPMorgan Chase and Co.’s diverse and critical businesses. You'll be using the latest technologies, data management, and security practices in all aspects of Infrastructure and software development. Critical thinking, clear communication, and collaboration are key to successful product delivery. Job responsibilities<ul><li>Executes creative solutions for the design, development, and technical troubleshooting for problems of high complexity</li><li>Applies technical expertise and problem-solving methodologies to projects of large scope</li><li>Drives a work stream or project consisting of one or more infrastructure engineering technologies</li><li>Works with other platforms to architect and implement changes required to resolve issues and modernize the organization and its technology processes</li><li>Strongly considers upstream/downstream data and systems or technical implications and advises on mitigation actions</li><li>Adds to team culture of diversity, equity, inclusion, and respect</li><li>Flexible to work in off hours/weekends &amp; in 24x7 on-call rotation.</li></ul> Required qualifications, capabilities, and skills<ul><li>Formal training or certification on infrastructure engineering concepts and 3+ years applied experience</li><li>Very good understanding in multiple infrastructure technologies and protocols including Global and Local load balancing, DNS, network routing, switching, firewalls and proxies.</li><li>Good knowledge and understanding of REST/JSON, API implementation and container based technologies.</li><li>Experience with programmatic methods of network device interaction, configuration and lifecycle management.</li><li>Thorough understanding of business technology drivers and their impact on architecture design, performance and monitoring, best practices.</li><li>Strong critical-thinking and problem-solving skills with clear communication.</li><li>Ability to collaborate with different teams and roles to achieve common goals.</li><li>Hands on experience with Atlassian products such as JIRA, Bitbucket, and Confluence.</li><li>Advanced knowledge and experience with network load balancing in F5 Load balancing technology (GTM, LTM, ASM, APM, AFM)</li><li>Extensive experience working in operations and troubleshooting complex configuration or device issues in Load balancing.</li><li>Experience working in CLI (command line interface) </li></ul> Preferred qualifications, capabilities, and skills<ul><li>F5 Certifications will be preferred but not desirable, like BIG-IP TMOS Administration (201) and LTM Technology Specialist (301)</li><li>Proficient in one programming language (ex. Python) and automation framework (Ansible)</li><li>Ability to multi-task across project/initiatives and deliver according to time commitments</li><li>Experience with Infrastructure as Code – IaC implementation. </li></ul><h4>Experience Level</h4>Senior Level

JP Morgan Services India Pvt Ltd

Technical Engineer

Engineering ExecutivePOSITION SUMMARY Install, maintain, perform preventative maintenance on, and recommend replacement of tools, appliances, and equipment. Calibrate all controls, gauges, meters, etc. Identify, locate, and operate all shut-off valves. Order, mark, and stock parts and supplies as needed. Maintain inventory and purchase orders log. Inspect tools, equipment, or machines. Enter and locate work-related information using computers. Operate power lift. Assist management in hiring, training, scheduling, evaluating, counseling, disciplining, and motivating and coaching employees; and serve as a role model. Follow all company and safety and security policies and procedures; report maintenance problems, safety hazards, accidents, or injuries; complete safety training and certifications; and properly store flammable materials. Ensure uniform and personal appearance are clean and professional. Anticipate and address guests’ service needs. Speak with others using clear and professional language and prepare and review written documents accurately and completely. Develop and maintain positive working relationships with others and listen and respond appropriately to the concerns of other employees. Ensure adherence to quality expectations and standards, and identify, recommend, develop, and implement new ways to increase organizational efficiency, productivity, quality, safety, and/or cost-savings. Move, lift, carry, push, pull, and place objects weighing less than or equal to 75 pounds without assistance. Move up and down stairs, service ramps, sloping, uneven, or slippery surfaces, and/or ladders. Reach overhead and below the knees, including bending, twisting, pulling, and stooping. Grasp, turn, and manipulate objects of varying size and weight. Stand, sit, or walk for an extended period of time. Perform other reasonable job duties as requested by Supervisors. PREFERRED QUALIFICATIONS Education: Technical, Trade, or Vocational School Degree.Related Work Experience: 4 to 6 years of related work experience.Supervisory Experience: No supervisory experience.  REQUIRED QUALIFICATIONSLicense or Certification: Valid Driver’s License  


  

At Marriott International, we are dedicated to being an equal opportunity employer, welcoming all and providing access to opportunity. We actively foster an environment where the unique backgrounds of our associates are valued and celebrated. Our greatest strength lies in the rich blend of culture, talent, and experiences of our associates. We are committed to non-discrimination on any protected basis, including disability, veteran status, or other basis protected by applicable law.<h4>Experience Level</h4>Executive Level

Marriott Hotels India

Engineering Manager

ROS Engineer Skills - C++ / Python, ROS, Linux, RTOSExperience - 2+ year Please Note:We will connect only with candidates whose profiles closely match our requirements and budget.

Delhivery

RO System Specialist

C++ Senior Technical Lead Qualifications:<ul><li>Looking for 8-10 years of work experience in C++, QT with QML</li><li>&nbsp;Good experience in UI Modelling Language QML and its integration with QT for user interface.</li><li>Should have experience in C++ and Object-oriented design.</li><li>Having good experience in SAFe Agile Methodology,</li><li>Knowledge on Git and Jenkin</li><li>Works collaboratively with agile team to implement and deliver quality solutions for applications with HMI.</li><li>Designs software components and modules using appropriate modelling techniques following agreed software design standards, patterns, and methodology.</li><li>Must have excellent communication skills.</li></ul>&nbsp;&nbsp;Description:<ul><li>We are looking for a C++ Developer with 8-10 years of rich experience to join our dynamic team for the frontend(QT\QML) and backend(C++) development.&nbsp;</li><li>Candidate should have&nbsp;experience in C++ programming, along with expertise in designing technical solutions.</li><li>Design, develop, and maintain high-quality C++ applications and QML for HMI.</li><li>Collaborate with cross-functional teams to define, design, develop and ship new features.</li><li>Debug and optimize existing code to improve performance and reliability.</li><li>Implement best practices for software development, including code reviews and unit testing.</li><li>Stay updated on the latest advancements in C++ and required technologies.</li><li>Technically lead squads with different modules and take ownership on the team deliveries.</li><li>Total Experience Expected: 08-10 years</li></ul> Education<ul><li>B.Tech</li></ul>

Sopra Steria India Limited

Senior Software Engineer

ASIC Engineer, IP Design, Silicon<h4>Minimum qualifications:</h4><ul><li>Bachelor’s degree in Electrical/Computer Engineering or equivalent practical experience.</li><li>3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation.</li><li>Experience with RTL design using Verilog/System Verilog and microarchitecture.</li><li>Experience with a scripting language like Python or Perl.</li></ul> <h4>Preferred qualifications:</h4><ul><li>Master's degree in Computer Science or Electrical Engineering.</li><li>6 years of industry experience with IP design.</li><li>Experience with methodologies for low power estimation, timing closure, and synthesis.</li><li>Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC).</li></ul><h4>About the job</h4>Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.<h4>Responsibilities</h4><ul><li>Define microarchitecture details, block diagram, data flow, pipelines, etc.</li><li>Perform RTL development (SystemVerilog), debug functional/performance simulations.</li><li>Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks.</li><li>Participate in synthesis, timing/power estimation and FPGA/silicon bring-up.</li><li>Communicate and work with multi-disciplined and multi-site teams.</li></ul><h4>Experience Level</h4>Mid Level

Google India Pvt Ltd

Associate - Engineering TechnicianAssociate - Engineering Technician-ANA018309Ready to shape the future of work?   At Genpact, we don’t just adapt to change—we drive it. AI and digital innovation are redefining industries, and we’re leading the charge. Genpact’s AI Gigafactory, our industry-first accelerator, is an example of how we’re scaling advanced technology solutions to help global enterprises work smarter, grow faster, and transform at scale. From large-scale models to agentic AI, our breakthrough solutions tackle companies’ most complex challenges.     If you thrive in a fast-moving, tech-driven environment, love solving real-world problems, and want to be part of a team that’s shaping the future, this is your moment.     Genpact (NYSE: G) is an advanced technology services and solutions company that delivers lasting value for leading enterprises globally. Through our deep business knowledge, operational excellence, and cutting-edge solutions – we help companies across industries get ahead and stay ahead. Powered by curiosity, courage, and innovation, our teams implement data, technology, and AI to create tomorrow, today. Get to know us at genpact.com and on LinkedIn, X, YouTube, and Facebook.    We are inviting applications for the role of Associate, Engineering Technician In this role you will be responsible for Make Ready Engineering (MRE) and Pole Loading Analysis (PLA) to help ensure that new utility pole attachments made by our customers meet utility standards and applicable codes. Responsibilities  <ul role="list"><li aria-setsize="-1" role="listitem">Determine if the existing pole configurations require Make Ready Engineering (MRE) for a new attachment per NESC/GO95 requirements.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Develop new attachment plan to address clearance violations.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Perform Pole Loading Analyses (PLA) of existing and proposed pole configurations.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Create Work Orders based on MRE and PLA results.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Review pole data collected in field for accuracy of existing attachments.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Manage assignments and meet/exceed production goals.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Use data/project management systems to document and track project progress.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Be willing to assist other Project Teams if work flow requirements dictate.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Track and report on progress of production projects. Track time spent on projects and maintain schedule.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Contribute to other related projects and plans not specifically noted necessary to obtain project objectives  </li></ul>  Qualifications we seek in you! Minimum qualifications  <ul role="list"><li aria-setsize="-1" role="listitem">Bachelor’s in engineering </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Basic understanding of databases and entering data using modern technology and software.  </li></ul><ul role="list"><li aria-setsize="-1" role="listitem"> Good years of related experience; Associate’s Degree in a related field preferred but not required </li></ul><ul role="list"><li aria-setsize="-1" role="listitem">Working knowledge of Microsoft Office products and effective and efficient use of modern computers  </li></ul>  Preferred qualifications <ul role="list"><li aria-setsize="-1" role="listitem">Overhead utility recognition experienc. </li></ul> Why join Genpact?   • Be a transformation leader – Work at the cutting edge of AI, automation, and digital innovation    • Make an impact – Drive change for global enterprises and solve business challenges that matter   • Accelerate your career — Get hands-on experience, mentorship, and continuous learning opportunities    • Work with the best – Join 140,000+ bold thinkers and problem-solvers who push boundaries every day    • Thrive in a values-driven culture – Our courage, curiosity, and incisiveness - built on a foundation of integrity and inclusion - allow your ideas to fuel progress    Come join the tech shapers and growth makers at Genpact and take your career in the only direction that matters: Up.   Let’s build tomorrow together.    Genpact is an Equal Opportunity Employer and considers applicants for all positions without regard to race, color, religion or belief, sex, age, national origin, citizenship status, marital status, military/veteran status, genetic information, sexual orientation, gender identity, physical or mental disability or any other characteristic protected by applicable laws. Genpact is committed to creating a dynamic work environment that values respect and integrity, customer focus, and innovation. Furthermore, please do note that Genpact does not charge fees to process job applications and applicants are not required to pay to participate in our hiring process in any other way. Examples of such scams include purchasing a 'starter kit,' paying to apply, or purchasing equipment or training.   <h4 xmlns:ftl="http://www.taleo.net/ftl" xmlns:htm="http://www.w3.org/1999/xhtml" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">Job</h4> Associate<h4 xmlns:ftl="http://www.taleo.net/ftl" xmlns:htm="http://www.w3.org/1999/xhtml" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">Primary Location</h4> India-Chennai<h4 xmlns:ftl="http://www.taleo.net/ftl" xmlns:htm="http://www.w3.org/1999/xhtml" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">Schedule</h4> Full-time<h4 xmlns:ftl="http://www.taleo.net/ftl" xmlns:htm="http://www.w3.org/1999/xhtml" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">Education Level</h4> Bachelor's / Graduation / Equivalent<h4 xmlns:ftl="http://www.taleo.net/ftl" xmlns:htm="http://www.w3.org/1999/xhtml" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">Job Posting</h4> Sep 1, 2025, 10:58:05 AM<h4 xmlns:ftl="http://www.taleo.net/ftl" xmlns:htm="http://www.w3.org/1999/xhtml" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">Unposting Date</h4> OngoingMaster Skills List OperationsJob Category Full Time<h4>Experience Level</h4>Mid Level

Genpact

Equipment Technician

Senior Standard Cell Designer<h4>
 
 General Information
 </h4>






 Job Title
 

 Senior Standard Cell Designer
 



 Job ID
 

 8804
 



 Country
 

 India
 



 City
 

 Hyderabad
 



 Date Posted
 

 17-Jan-2025
 



 Job Category
 

 Engineering
 



 Job Subcategory
 

 R&amp;D Engineering
 



 Hire Type
 

 Employee
 



 Remote Eligible
 

 No
 






<h4>
 
 Descriptions &amp; Requirements
 </h4>






 Job Description and Requirements
 

<h4 id="isPasted">Alternate Job Titles:</h4><ul><li>Senior Cell Library Design Engineer</li><li>Senior Logic Library Design Engineer</li><li>Senior Standard Cell Designer</li></ul><h4>We Are:</h4>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.<h4>You Are:</h4>You are an experienced Standard Cell Library Design Engineer with a passion for innovation and technology. You hold a Bachelor's or Master's degree from a reputable university and have over three years of experience in designing standard cell libraries. Your expertise extends to optimizing standard cell circuits to achieve superior performance, power, and area (PPA). You have designed complex circuits such as flip-flops, clock gating cells, level shifters, and power gating cells. Your deep understanding of CMOS device characteristics and design rules in submicron process nodes, especially in FINFET/GAA technologies, sets you apart. You are proficient in running high sigma variation analysis and have a knack for layout design and optimization. Your analytical and logical skills are exemplary, and you thrive in a collaborative environment, working effectively with geographically distributed R&amp;D teams. If you are driven by innovation and eager to contribute to groundbreaking technology, we want to meet you.<h4>What You’ll Be Doing:</h4><ul><li>Designing and optimizing standard cell libraries to achieve targeted PPA.</li><li>Developing complex circuits including flip-flops, clock gating cells, level shifters, and power gating cells.</li><li>Collaborating with layout designers to optimize layout parasitics.</li><li>Engaging in layout extraction and understanding layout-dependent parameters.</li><li>Conducting timing and power characterization of standard cells.</li><li>Working closely with cross-functional teams for optimization across the design chain.</li></ul><h4>The Impact You Will Have:</h4><ul><li>Enhancing the performance, power, and area of standard cell libraries.</li><li>Contributing to the development of high-impact, cutting-edge technology.</li><li>Driving innovation in complex circuit design and optimization.</li><li>Ensuring the successful integration of IP blocks into SoCs.</li><li>Influencing the design and development of self-driving cars, AI, and IoT devices.</li><li>Supporting Synopsys’ leadership in the silicon IP market.</li></ul><h4>What You’ll Need:</h4><ul><li>Bachelor's or Master's degree in Electrical Engineering or related field.</li><li>3+ years of experience in standard cell library design.</li><li>Expertise in CMOS device characteristics and submicron process nodes.</li><li>Proficiency in designing complex circuits and running high sigma variation analysis.</li><li>Experience in layout design and optimization.</li></ul><h4>Who You Are:</h4><ul><li>Strong analytical and logical thinker.</li><li>Detail-oriented with excellent problem-solving skills.</li><li>Effective communicator and collaborator.</li><li>Innovative and passionate about technology.</li><li>Adaptable and able to work in a dynamic, fast-paced environment.</li></ul><h4>The Team You’ll Be A Part Of:</h4>You will join the Logic Library Group, a dynamic team focused on developing high-performance standard cell libraries. The team collaborates closely with other R&amp;D groups to optimize the entire design chain and deliver cutting-edge technology solutions. Together, you will work on innovative projects that drive the future of chip design and integration.<h4>Rewards and Benefits:</h4>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.<h4>Experience Level</h4>Senior Level

Electrical Design Engineer

Full Stack Architect <ul><li>Lead innovation with Vue.js, Node.js, Python, and cloud-native tools like Docker, Kubernetes, Helm, and Kafka.</li><li>Build high-performance, scalable applications, design APIs, and manage multi-environment deployments.</li><li>Short joiners preferred</li></ul> Share your updated resume now.

Live Connections

Full Stack Engineer

Network DeveloperThe AI2NE Org strives to be global leaders in the RDMA cluster networking domain and enable seamless, accelerated High-Performance Compute (HPC), Artificial Intelligence and Machine Learning advancements. We envision a future where artificial intelligence and machine learning revolutionize industries, reshape societies, and unlock limitless possibilities. Our vision is to be a pioneering force, driving the development and design of state-of-the-art RDMA clusters tailored specifically for AI, ML, HPC workloads. We strive to be the go-to experts in RDMA cluster architecture, leveraging our deep understanding of the unique demands of AI/ML and HPC applications. By staying at the forefront of technological advancements, we aim to redefine the boundaries of what is possible, pushing the envelope of computational capabilities and unlocking unprecedented performance. Supports the design, deployment, and operations of a large-scale global Oracle Cloud Infrastructure (OCI). Primarily focused on the development and support of network fabric and systems through a combination of a deep level understanding of networking at the protocol level coupled with programming skills. As OCI is a cloud-based network with a global footprint, this support will include hundreds of thousands of network devices supporting millions of servers, connected over a mix of dedicated backbone infrastructure, CLos Network, and the Internet.<ul><li>Will primarily use existing procedures and tools to develop and safely execute network change. However, may have to develop new procedures from time to time.</li><li>Develop solutions to enable front line support teams to act on network failure conditions. </li><li>Participate in operational rotations as either primary or secondary. </li><li>Provide break-fix support for events. Serve as the escalation point for event remediation. Participate post-event root cause analysis.</li><li>Frequently develops scripts to automate routine tasks for team and business units. </li><li>Coordinate with networking automation services for the development and integration of support tooling. </li><li>Coordinate with network monitoring to gather telemetry and create alerts rules using them.</li><li>Build dashboards to represent data at various network layers and device roles that help identify network issues, anomalies. </li><li>Collaborate with network vendor technical account team and internal Quality Assurance team to drive bug resolution and assist in the qualification of new firmware and/or operating systems.        </li><li> </li><li>Qualifications:<ul><li>Bachelor’s degree in CS or related engineering field with 2+ years of Network Engineering experience or master’s with 1+ years of Network Engineering experience.</li><li>Experience working in a large ISP or cloud provider environment. Experience in RDMA Networking is a plus.</li><li>Experience working in a network operations role.</li><li>Folks with knowledge of routing protocols such as knowledge of TCP/IP, IPv4, IPv6, DNS, DHCP and SSL.</li><li>Experience with scripting or automation and data center design – Python preferred but must demonstrate expertise in scripting or compiled language.</li><li>Experience with network monitoring and telemetry solutions.</li><li>Experience with network modeling and programming – YANG, OpenConfig, NETCONF.</li><li>Ability to use professional concepts and company objectives to resolve issues in creative and effective ways.</li><li>Excellent organizational, verbal, and written communication skills.</li><li>Participate in an on-call rotation.                                                                                                                                                                                                                                                        </li></ul></li></ul>Career Level - IC2As a world leader in cloud solutions, Oracle uses tomorrow’s technology to tackle today’s challenges. We’ve partnered with industry-leaders in almost every sector—and continue to thrive after 40+ years of change by operating with integrity. We know that true innovation starts when everyone is empowered to contribute. That’s why we’re committed to growing an inclusive workforce that promotes opportunities for all.Oracle careers open the door to global opportunities where work-life balance flourishes. We offer competitive benefits based on parity and consistency and support our people with flexible medical, life insurance, and retirement options. We also encourage employees to give back to their communities through our volunteer programs.We’re committed to including people with disabilities at all stages of the employment process. If you require accessibility assistance or accommodation for a disability at any point, let us know by emailing <a href="mailto:accommodation-request_mb@oracle.com" rel="nofollow" target="_blank">accommodation-request_mb@oracle.com</a> or by calling +1 888 404 2494 in the United States. Oracle is an Equal Employment Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability and protected veterans’ status, or any other characteristic protected by law. Oracle will consider for employment qualified applicants with arrest and conviction records pursuant to applicable law. <h4>Experience Level</h4>Mid Level

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