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Linux Device Driver Developer Capgemini is hiring for Linux Device Driver Developer (LDD) can join in 30 Days, and possess the required skill set, apply to this job. Experience: 4- 10 years Key Requirements:1. 3-5 Yrs of experience in Embedded Linux Kernel/Drivers domain2. Embedded Software development and porting on Linux and ARM platforms3. Strong Programming skills on C &amp; Data Structures4. Expertise on OS (Memory Mgmt, Scheduling, IPC, Multi-threading/processing)5. Experience in Linux Kernel/Device Drivers6. Proficiency in debugging embedded systems, including using tools like JTAG7. Understanding of System architecture and debugging at a system level. Please send your resume with the following details:Subject Line: Job Application- LDD (Linux Device Drivers)Name:Total Exp:Rel exp:Current CTC:ECTC:Current location:Are you willing to relocate?Notice period/ LWD:

Capgemini

Linux Engineer

BIM Coordinator We’re seeking talented minds&nbsp;who thrive on clarity, collaboration, and long-term impact. Step into work that matters. • Experience - 8+ years What You'll Gain• Projects at grand scale.• Guidance that sharpens your craft.• A culture that balances creativity with growth. Send your updated CV &amp; portfolio&nbsp;now.

Edifice Consultants

Senior Architect

STA Engineer Digicomm Semiconductor is seeking talented STA Engineers with hands-on experience in PrimeTime and PT-ECO for block-level timing analysis and closure. Key Skills &amp; Responsibilities:<ul><li> Expertise in block-level timing constraints enablement &amp; analysis</li><li> Strong clocking and data flow understanding</li><li> Proficient in check_timing, QoR checks, and constraints validation</li><li> Collaborate with physical design teams for block-level timing closure</li><li> Good understanding of CTS build &amp; clock tree specifications</li><li> Experience with timing ECOs and final timing sign-off</li><li> Scripting skills in Tcl, Unix</li></ul> Experience: 3–6 Years Share your updated resume now.

Digicomm Semiconductor

Associate Engineer

STA Engineer – Tempus Expert Digicomm Semiconductor is looking for an experienced STA Engineer with strong expertise in Tempus-based timing analysis and closure for advanced SoC designs. Key Skills:<ul><li>&nbsp; Expert in STA flow setup and cleanup</li><li>&nbsp; Hands-on Timing fixes using Tempus</li><li>&nbsp; Strong understanding of timing constraints and exceptions</li><li> Good communication and cross-domain collaboration skills</li><li> A proactive team player</li></ul> Experience: 6–12 Years Share your updated resume now.

Senior Design Verification Engineer Key Skills:<ul><li> System Verilog, UVM/OVM, Verilog</li><li> AMBA, Bluetooth MAC, Wi-Fi 802.11 MAC</li><li> Low Power Verification (UPF), simulation &amp; debug</li><li> Testbench development &amp; coverage analysis</li><li> Scripting – Perl, Shell, or similar</li></ul> <ul><li>Experience: 7+ Years</li><li>Qualification: MS/B.E/B.Tech in EE/EC</li></ul> Share your updated resume now.

Assistant Design Engineer

RTL & GLS Verification Engineer – Turing Subsystem Digicomm Semiconductor is looking for an experienced RTL &amp; GLS Verification Engineer to join our dynamic verification team working on Turing Subsystem Verification. Mandatory Skills:<ul><li> System Verilog / UVM</li><li> AHB, AXI protocol knowledge</li><li> Strong coding &amp; debugging skills</li><li> GLS (Gate-Level Simulation) verification</li><li> Formal / Power-Aware Verification (UPF-based)</li></ul> Roles &amp; Responsibilities:<ul><li>Own and execute Turing subsystem verification</li><li>Perform RTL and GLS functional + low-power verification</li><li>Drive regression closure for subsystem verification and GLS regressions</li><li>Collaborate with design and cross-functional teams for issue resolution</li></ul> Experience: 3+ Years Share your updated resume now.

Testing Engineer

Power & System Validation Engineer Key Responsibilities: • Execute and analyze CPU/GPU/AI-ML workloads and benchmarks on Android &amp; Windows platforms • Measure and interpret power, thermal, and performance KPIs across SoC subsystems (CPU, NPU, DDR, etc.) • Automate data collection, parsing &amp; reporting using Python, Shell, or Batch scripts • Perform validation, debugging, and optimization for performance/power efficiency • Operate lab instruments like oscilloscopes, power analyzers &amp; thermal tools Requirements: • Strong understanding of SoC architecture &amp; subsystems • Experience in power/performance validation and automation scripting • Exposure to MLPerf, GenAI, or vision workloads is a plus • Experience: 4–8 Years Share your updated resume now.

Test Engineer

Verification EngineerThe Verification Engineer will be responsible for ensuring the quality and reliability of hardware and network systems. They will work closely with the engineering team to develop and execute verification plans, analyze test results, and identify and resolve any issues. The role requires strong problem-solving skills, attention to detail, and the ability to work effectively in a team environment.

eInfochips ( An Arrow Company )

RTL Design Engineer Key Skills:<ul><li> RTL design &amp; micro-architecture (Verilog/System Verilog)</li><li> Wireless protocols – Wi-Fi (802.11 a/b/g/n/ac/ax/be), LTE, 5G NR</li><li> Bus protocols – AXI, AHB, APB</li><li> Low-power design, CDC handling</li><li> Tools – Spyglass, 0-in, Design Compiler, Prime Time</li><li> SoC integration &amp; post-silicon debug</li></ul> <ul><li>Experience: 2–15 years</li><li>Domain: Digital Front-End ASIC Design</li></ul> Share your updated resume now.

Electronic Engineer

Hardware Design Engineer As a Hardware Design Engineer at Netweb Technologies, you will be responsible for project deliverables, including detailed design specifications, schematics, and Bill of Materials (BOM). You will collaborate with cross-functional teams, understand the design requirements, design the system/subsystem, and actively participate in design reviews.<ul><li>Design Schematics: You will be responsible for designing schematics of digital, mixed-signal, and power electronics circuits that meet the design requirements.</li><li>PCB Layout Interaction: You will work with PCB layout teams to finalize component placement, considering Mechanical and Signal Integrity/Power Integrity (SI/PI) constraints.</li><li>Component Selection: You will be involved in the component selection process and work with vendors to finalize components that meet the design requirements.</li></ul> Work Expereince<ul><li>5-8 years</li></ul> Qualifications<ul><li>Experience: You should have at least 3 to 6 years of experience in hardware development life-cycle, from design conception to board bring-up and testing.</li><li>Board Design Fundamentals: Strong knowledge of Mixed signal design, High-Speed board design, and Power Design.</li><li>Microprocessors: Experience in working with different embedded microprocessors based on Qualcomm, TI, NXP, NVIDIA, Intel, and AMD.</li><li>Communication Protocols: Proficiency in designing interfaces with Bus communication protocols like I2C, SPI, UART, RS232.</li><li>High-Speed I/Os: Experience with High-Speed I/Os such as PCIe, Memory (DDRx, LPDDRx), MIPI C-PHY/D-PHY, USB3.0/USB4.0, and Ethernet interfaces.</li><li>EDA Tools: Expertise in using EDA tools for schematics and layout, mainly Cadence PCB tools.</li><li>Simulation Tools: Experience with simulation tools like PSPICE/LTSPICE.</li><li>Lab Experience: Hands-on lab experience using Oscilloscopes, Digital Multimeters (DMM), spectrum analyzers, and Debugger tools.</li><li>SI/PI Knowledge: Fundamental knowledge of Signal Integrity and Power Integrity.</li><li>Additional Advantage: Experience with any of the SI/PI simulation tools like Hyperlynx, Sigrity, Ansys, and ADS.</li><li>EMI/EMC Standards: Good knowledge of EMI/EMC standards for industrial, Class A products.</li></ul> Education<ul><li>Bachelor's or Master's degree in Electronics.</li></ul>

Netweb Technologies

Hardware Engineer

DFT Engineer Digicomm Semiconductor is looking for an experienced DFT Engineer with strong expertise in ASIC test methodologies. Key Requirements:<ul><li>Hands-on with MBIST, scan insertion, ATPG, DRC analysis &amp; resolution</li><li>Experience in test coverage improvement and hierarchical test</li><li>Strong debugging skills and familiarity with PD/Timing collaterals</li><li>Proficient in Synopsys tools – TestMax Manager, TestMax ATPG, TestMax Advisor, VCS</li></ul> Experience: 6+ Years Share your updated resume now.

Staff Engineer, VLSI Design Engineering<h4>Company Description</h4>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.<h4>Job Description</h4> Actively contribute to provide Custom Datapath solutions for next generation Memory in advanced CMOS technology nodes.Designing Datapath (custom and/or RTL) Blocks, Full chip Timing Finesim Design closure to meet the specifications and product requirementsWork closely with team and actively participate in technical discussions and reviews.Pro-actively get design issues/problems solved.Contribute to or propose innovative design solutions and design methodologies. <h4>Qualifications</h4><ul><li>Bachelors/Masters degree in Electronics &amp; Telecommunication/Electrical engineering  (VLSI Design)</li><li>Hands-on design knowledge on both Digital custom, Analog &amp; mixed signal design environment.</li><li>4+ years of Experience on IO circuit blocks used in memory products like DDR4, DDR5, LPDDR4, LPDDR5, GDDR5, GDDR6 is desirable.</li><li>NAND Flash Design knowledge is plus</li><li>Familiar with custom design methodology &amp; flow, Calibration, JTAG design requirements, understanding of High-speed IO circuit and Datapath design including  DLL, Rx, Tx and clocking circuits</li><li>Knowledge of High Speed layout guidelines, analog layout techniques, including floor-planning, matching, shielding and parasitic optimization</li><li>Understanding Datapath circuits like pipelining, digital design, STA, fan-out and load estimation, FIFO design etc..</li><li>Familiarity with package/board/Power integrity /signal integrity constraints is a plus.</li><li>Strong communication skills &amp; circuit design knowledge is preferred.</li><li>Tool knowledge: spice tools: finesim, hspice &amp; other flows</li><li>Good automation &amp; scripting knowledge is plus.</li></ul><h4>Additional Information</h4>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at <a href="mailto:jobs.accommodations@sandisk.com">jobs.accommodations@sandisk.com</a> to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying. <h4>Experience Level</h4>Senior Level

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