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<p>CAA Developer</p><p><br></p><p>Join our team as a CAA Developer.</p><p>&nbsp;<strong>Experience</strong>: 4 to 10 Years&nbsp;</p><p><br></p><p>-Expertise in CATIAV5 automation using macros (VB/VBA) </p><p>-Experience with CAD customization and integration </p><p>-Expertise in CAA development </p><p>-Familiarity with Teamcenter integration with CATIA is a plus </p><p>-Proficient in CAA RADE development for CATIA V5 </p><p>-Strong C++ programming skills </p><p>-Experience in CATIA V5 APIs and customization </p><p>-Integration experience with engineering tools or data sources </p><p>-Developer must be self-managed and capable of working with minimal supervision. </p><p>-Ability to gather requirements independently from stakeholders. </p><p>-Must coordinate effectively with peers from team. </p><p>-Should be proactive in communication, status reporting, and issue resolution.&nbsp;</p><p><br></p><p>Interested candidates can share their resume.</p>

L&T Technology Services Ltd

SQL Developer

Sector 29 Chandigarh

Kalka Panchkula

This is calling bases job :- candidate should be good in communication.
Basic knowledge about digital platforms.
If can communicate in regional language
Time requirement : 5-6 hours minimum


Reliance Jio

Freelancer

<p>Sr.Engineer, Stack</p><b>What you need :</b><br/>• Development experience on Cellular Radio products complying to 3GPP specification for E-UTRA (LTE) and NR• Familiar with communication interfaces Ethernet / TCP/IP / UDP .• Should have good knowledge on RAN protocol and interfaces. o LTE/5G  AS protocol  layers - PHY, MAC, RLC, PDCP, RRC• Excellent Log analysis and debugging skills.• Must be strong in C/C++ Programming and Linux OS.• Hands on experience on debugging in Linux environment with tools like GDB, QXDM, TM500, QCAT etc.• Good to have experience of Git.
<h4>What you will do </h4><ul><li>Developing Cellular Radio products complying to 3GPP specification for E-UTRA (LTE) and NR</li><li>Coding in Linux environment across layer3 and layer2 protocols.  </li><li>Working with Git in Linux environment</li><li>Log analysis and debugging of customer defects and internal QA issues.</li><li>Log analysis using tools like GDB, QXDM, TM500, QCAT etc.</li></ul><h4>Experience Level</h4>Senior Level

PARALLEL WIRELESS INDIA PRIVATE LIMITED

Full Stack Engineer

<p>Staff Engineer (Memory Circuit Design)</p><h4>Company Description</h4><p>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.</p><p>Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.</p><p>Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.</p><h4>Job Description</h4><p>Responsibilities include:</p><ul><li>In this position the individual will be responsible for designing, modifying and evaluating CMOS circuit structures for the most advanced high-performance low-power 3-dimensional NAND flash memory</li><li>Verify designs in simulation and interact with layout, logic and other functional groups for implementation, full chip integration and silicon validation.</li><li>Evaluation of these circuits will be done through FINESIM and VERILOG simulations.</li><li>Collaborate with characterization engineers to fully characterize silicon, and partner with other designers to develop solutions for silicon issues</li><li>Responsible for full chip silicon evaluation through probing.</li><li>Interact with Memory Device team for transistor models, EDR/GDR requirements and tradeoffs.     </li><li>CMOS transistor level design, simulation, layout knowledge of common custom circuits like amplifiers, current mirrors, level shifters, switches, decoders.</li><li>Knowledge of running and debugging Verilog simulations</li><li>Good understanding of Solid-State device physics.</li><li>Comfortable with IC tools such as Cadence analog design environment, HSPICE/FINESIM, VCS/EXCELIUM, UNIX.</li><li>Ability to troubleshoot and analyze complex problems.</li><li>Excellent communication skills to effectively collaborate with Off-site counterparts across global teams</li></ul><h4>Qualifications</h4><ul><li>B.E./B.Tech/M.E/M.S/M.Tech in electronics branches</li><li>Aggregate of 75% &amp; Above in all qualifying exams</li><li> 4+ years of relevant Industry Experience</li></ul><h4>Additional Information</h4><p>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.</p><p>Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at <a href="mailto:jobs.accommodations@sandisk.com">jobs.accommodations@sandisk.com</a> to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.</p><h4>Experience Level</h4>Senior Level

SanDisk India Device Design Centre Pvt.Ltd

Trainee Engineer

<p>Memory Layout Engineer - Staff</p><h4>
                
                General Information
            </h4>






                                                Job Title
                                            

                                                                                            Memory Layout Engineer - Staff
                                                                                    



                                                Job ID
                                            

                                                                                            12499
                                                                                    



                                                Country
                                            

                                                                                            India
                                                                                    



                                                City
                                            

                                                                                            Hyderabad
                                                                                    



                                                Date Posted
                                            

                                                                                            07-Aug-2025
                                                                                    



                                                Job Category
                                            

                                                                                            Engineering
                                                                                    



                                                Job Subcategory
                                            

                                                                                            Layout Design
                                                                                    



                                                Hire Type
                                            

                                                                                            Employee
                                                                                    



                                                Remote Eligible
                                            

                                                                                            No
                                                                                    






<h4>
                
                Descriptions &amp; Requirements
            </h4>






                                                Job Description and Requirements
                                            

<p><br/></p><p><strong>You Are:</strong></p><p>You are an experienced Memory Layout Design Engineer with a passion for developing cutting-edge technology. You possess a Bachelor’s or Master’s degree in Electronics Engineering, Telecommunication, Physics, or related fields. With a minimum of 6 years of experience in layout design, you have advanced knowledge of Custom Layout and a deep understanding of Embedded Memory Layout. Your strong communication, documentation, and analytical skills enable you to collaborate effectively with cross-functional teams. You are detail-oriented, proactive, and thrive in a dynamic environment where innovation and continuous improvement are paramount.</p><p><strong>What You’ll Be Doing:</strong></p><ul><li>Design, develop, and modify layout designs for Embedded Memory IPs.</li><li>Improve and determine methods and procedures for layout development flow to ensure efficiency and accuracy.</li><li>Collaborate with design engineers to optimize layout designs for performance and manufacturability.</li><li>Conduct layout verification and ensure compliance with design rules and specifications.</li><li>Provide technical guidance and mentorship to junior layout engineers.</li><li>Stay updated with the latest industry trends and technologies to incorporate best practices in layout design.</li></ul><p><strong>The Impact You Will Have:</strong></p><ul><li>Enhancing the performance and reliability of our Embedded Memory IPs and other foundational IPs.</li><li>Contributing to the efficiency and effectiveness of our layout development processes.</li><li>Ensuring high-quality and manufacturable layout designs that meet industry standards.</li><li>Supporting the seamless integration of our IPs into customer designs, accelerating their time-to-market.</li><li>Driving innovation in layout design and setting new benchmarks for excellence in the industry.</li><li>Fostering a culture of continuous improvement and technical excellence within the team.</li></ul><p><strong>What You’ll Need:</strong></p><ul><li>Bachelor’s or Master’s degree in Electronics Engineering, Telecommunication, Physics, or related fields.</li><li>Minimum of 6 years of experience in Memory layout design.</li><li>Advanced knowledge of Custom Layout and a deep understanding of Embedded Memory Layout.</li><li>Strong communication, documentation, and analytical skills.</li><li>Proficiency in layout verification tools and methodologies.</li><li>Scripting knowledge in python and/or TCL is highly preferred</li></ul><p><strong>Who You Are:</strong></p><ul><li>Detail-oriented and meticulous in your work.</li><li>Proactive and able to work independently as well as part of a team.</li><li>Excellent problem-solving skills and the ability to think critically.</li><li>Adaptable and open to learning new technologies and methodologies.</li><li>A strong communicator who can effectively collaborate with cross-functional teams.</li></ul><p><strong>The Team You’ll Be A Part Of:</strong></p><p>You will be part of a dynamic and innovative team focused on developing high-performance silicon IPs. Our team collaborates closely with design engineers, verification engineers, and other stakeholders to deliver best-in-class solutions. We are committed to continuous learning and improvement, fostering an environment where creativity and technical excellence thrive.</p><p><strong>Rewards and Benefits:</strong></p><p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p><p><br/></p><p><span id="isPasted">At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</span></p><h4>Experience Level</h4>Senior Level

Synopsys India Pvt Ltd

Computer Engineer

<p>Engineering Manager  - FlashArray</p><p>We’re in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry.</p><p>This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.</p><p>We’re in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry.</p><p>This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.</p><h4>Should You Accept This Challenge…</h4><p>Pure Storage is seeking an Engineering Manager to lead the Feature, Insights &amp; Tools team  at Pure, responsible for developing and scaling the automated test infrastructure for our all-flash storage solutions. This role requires a hands-on leader with a passion for improving efficiency, streamlining build-test pipelines, and driving faster development cycles.</p><p>As an Engineering Manager, you will:</p><ul><li>Lead a team of talented software engineers based in Bangalore, improving build-test pipelines to enable faster feature delivery.</li><li>Collaborate with global teams, including product management, feature teams, and release teams, to optimize automation strategies.</li><li>Work with key stakeholders across multiple global locations, including Bangalore, Prague, and Santa Clara HQ.</li><li>Drive automation strategies, ensuring scalable, resilient, and deterministic pipelines that seamlessly integrate into CI/CD workflows.</li><li>Address test flakiness, enhance pipeline stability, and improve test determinism, reducing delays in feature rollouts.</li><li>Lead by example, contributing hands-on to design, development, debugging, and making development pipelines robust.</li><li>Mentor and develop engineers, fostering technical excellence and career growth.</li><li>Define and leverage key metrics to refine automation processes, track efficiency improvements, and optimize release cycles.</li></ul><h4>What You’ll Bring To The Team…</h4><ul><li>BS in Computer Science or equivalent experience</li><li>3+ years of technical management experience, leading software engineers while remaining hands-on with software development, test automation, and troubleshooting.</li><li>10+ years of software development experience in Python, Golang, or similar languages, with expertise in microservices, REST APIs, pytest, and developer tooling.</li><li>Proven expertise in managing projects throughout the software development lifecycle (SDLC)</li><li>Deep understanding of automated test frameworks, CI/CD pipelines, and scalable build-test automation</li><li>Experience in troubleshooting and managing complex automation systems</li><li>Ability to foster collaboration across software and Hardware teams to enhance developer efficiency</li><li>Demonstrated leadership and problem-solving skills in scaling test infrastructure, building tools, microservices, and improving pipeline performance</li><li>Experience working with cross-functional teams and global stakeholders, ensuring effective communication and alignment with teams in Bangalore, Prague, and Santa Clara HQ.</li><li>Excellent written and verbal communication skills, with the ability to present technical concepts to executive stakeholders</li></ul><p>At Pure Storage, we believe in continuous improvement, ownership, and innovation. If you are passionate about building world-class automation frameworks, optimizing development workflows, and accelerating feature delivery, we’d love to hear from you!</p><p><strong>WHAT YOU CAN EXPECT FROM US:</strong></p><ul><li><strong>Pure Innovation</strong>: We celebrate those who think critically, like a challenge and aspire to be trailblazers.</li><li><strong>Pure Growth</strong>: We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area™, Fortune's Best Workplaces for Millennials™ and certified as a Great Place to Work®!</li><li><strong>Pure Team</strong>: We build each other up and set aside ego for the greater good.</li></ul><p>And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out <a href="http://purebenefits.com">purebenefits.com</a> for more information.</p><p><strong>ACCOMMODATIONS AND ACCESSIBILITY:</strong></p><p>Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at <a href="mailto:TA-Ops@purestorage.com">TA-Ops@purestorage.com</a> if you’re invited to an interview.</p><p><strong>OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM:</strong></p><p>We’re forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn’t just accepted but embraced. That’s why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership.<br/><br/>Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.</p><h4>Experience Level</h4>Mid Level

Pure Storage India Pvt Ltd

Engineering Manager

<p>Member Of Technical Staff-Drive FW Validation Engineer</p><p>We’re in an unbelievably exciting area of tech and are fundamentally reshaping the data storage industry. Here, you lead with innovative thinking, grow along with us, and join the smartest team in the industry.</p><p>This type of work—work that changes the world—is what the tech industry was founded on. So, if you're ready to seize the endless opportunities and leave your mark, come join us.</p><p>BE PART OF BUILDING THE FUTURE.</p><p>What do NASA and emerging space companies have in common with COVID vaccine R&amp;D teams or with Roblox and the Metaverse? </p><p>The answer is data, -- all fast moving, fast growing industries rely on data for a competitive edge in their industries. And the most advanced companies are realizing the full data advantage by partnering with Pure Storage. Pure’s vision is to redefine the storage experience and empower innovators by simplifying how people consume and interact with data. <a href="https://www.purestorage.com/content/dam/purestorage/pdf/PureStorage_FactSheet.pdf.">With 11,000+ customers including 58% of the Fortune 500, we’ve only scratched the surface of our ambitions</a>. </p><p>Pure is blazing trails and setting records:</p><ul><li>For nine straight years, Gartner has named Pure a leader in the Magic Quadrant </li><li>Our customer-first culture and unwavering commitment to innovation have earned us a certified Net Promoter Score in the top 1% of B2B companies globally</li><li>Industry analysts and press <a href="https://www.purestorage.com/company/newsroom/awards.html">applaud Pure’s leadership</a> across these dimensions</li><li>And, our 5,000+ employees are emboldened to make Pure a faster, stronger, smarter company as we go</li></ul><p>If you, like us, say “bring it on” to exciting challenges that change the world, we have endless opportunities where you can make your mark.</p><p><strong>SHOULD YOU ACCEPT THIS CHALLENGE...</strong></p><p>The DFM Firmware Team plays a crucial role in designing and developing the Direct Flash Module (DFM) – a key module of Pure's Flasharray and Flashblade enterprise storage solutions. The DFM is an internally designed enterprise storage device using the NAND flash technology. Compared with the off-the-shelf SSD, the DFM has the competitive advantage of  simplicity, high performance, low cost and scalability.</p><p>As a member of the DFM team, you’ll be actively engaged in all phases of the product development cycle with a focus on validation of the various FW modules. You will be involved in analysing the existing tests and enhancing/adding the new test cases to ensure end to coverage of the FW design with a key focus on the exception/error scenarios. You would be also responsible for developing the FW regression test suite which would be used for nightly/weekly runs and helps in assessing the FW stability for the regular and milestone specific FW releases. </p><p><strong>What You Will Be Doing</strong></p><p>Pure Storage is seeking a full-time Firmware Validation Engineer to join our device firmware team. You will be working as part of a small, but fast growing, dynamic team and will be responsible for:</p><ul><li>Implementing firmware test for Pure Storage’s DirectFlash™ SSD Modules</li><li>Investigating and debugging issues, and developing failure analysis tools and process</li><li>Coding and testing in C/C++ and Python</li><li>Develops and delivers the firmware verification tests for various firmware SSD/NAND features and enhance the regression test suite</li><li>Internal development automation including continuous integration, automated unit and regression testing, etc</li><li>Working closely with hardware, system software and manufacturing teams</li></ul><p>The ideal candidate would be someone who is a team player and perceived as highly skilled in test development/debugging for hardware/firmware/system validation needs..</p><p><strong>What You Bring to the Team</strong></p><ul><li>8+ years experience developing software to validate hardware components/systems with strong SW &amp; HW debug skills</li><li>Strong knowledge of NAND Flash, Firmware Architecture/Design in Solid State Drive (SSD) or similar storage domain</li><li>Scripting experience in Python with exposure to OOP; C++ experience is a plus.</li><li>Experience in a hardware testing/software testing validation lab for SSDs or Embedded industry segments</li><li>B.E. or M.E in Electrical Eng, Electronics &amp; Communication Eng, Computer Eng</li><li>Experience working at enterprise data storage systems, SSD companies or related component vendors.</li><li>Independent ability to devise, implement, automate and refine qualification methods</li><li>Strong knowledge of hardware design, storage architectures and storage interfaces.</li><li>Experience with failure modes of flash-based devices</li><li>Good verbal communication &amp; collaboration skill.</li><li>Must be willing and able to work in an open office, team environment.</li></ul><p><strong>WHAT YOU CAN EXPECT FROM US:</strong></p><ul><li><strong>Pure Innovation</strong>: We celebrate those who think critically, like a challenge and aspire to be trailblazers.</li><li><strong>Pure Growth</strong>: We give you the space and support to grow along with us and to contribute to something meaningful. We have been Named Fortune's Best Large Workplaces in the Bay Area™, Fortune's Best Workplaces for Millennials™ and certified as a Great Place to Work®!</li><li><strong>Pure Team</strong>: We build each other up and set aside ego for the greater good.</li></ul><p>And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources and company-sponsored team events. Check out <a href="http://purebenefits.com">purebenefits.com</a> for more information.</p><p><strong>ACCOMMODATIONS AND ACCESSIBILITY:</strong></p><p>Candidates with disabilities may request accommodations for all aspects of our hiring process. For more on this, contact us at <a href="mailto:TA-Ops@purestorage.com">TA-Ops@purestorage.com</a> if you’re invited to an interview.</p><p><strong>OUR COMMITMENT TO A STRONG AND INCLUSIVE TEAM:</strong></p><p>We’re forging a future where everyone finds their rightful place and where every voice matters. Where uniqueness isn’t just accepted but embraced. That’s why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership.<br/><br/>Pure is proud to be an equal opportunity and affirmative action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.</p><h4>Experience Level</h4>Senior Level

Embedded Software Developer

<p>Sr Director Analog Design</p><h4>
                
                General Information
            </h4>






                                                Job Title
                                            

                                                                                            Sr Director Analog Design
                                                                                    



                                                Job ID
                                            

                                                                                            10566
                                                                                    



                                                Country
                                            

                                                                                            India
                                                                                    



                                                City
                                            

                                                                                            Bengaluru
                                                                                    



                                                State/Province
                                            

                                                                                            Karnataka
                                                                                    



                                                Date Posted
                                            

                                                                                            08-Apr-2025
                                                                                    



                                                Job Category
                                            

                                                                                            Engineering
                                                                                    



                                                Job Subcategory
                                            

                                                                                            Analog Design
                                                                                    



                                                Hire Type
                                            

                                                                                            Employee
                                                                                    



                                                Remote Eligible
                                            

                                                                                            No
                                                                                    






<h4>
                
                Descriptions &amp; Requirements
            </h4>






                                                Job Description and Requirements
                                            

<h4 id="isPasted">We Are:</h4><p>At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.</p><h4>You Are:</h4><p>You are a brilliant and accomplished technical expert in SERDES design, with a passion for pushing the boundaries of what is possible. You thrive in a collaborative environment, working alongside top-tier analog and mixed-signal design professionals. You bring a wealth of experience in developing high-speed transceiver architectures and have a proven track record of innovation in the field. You are driven by a desire to achieve best-in-class performance while minimizing power and area. Your extensive background in analog IC design and system architecture makes you an invaluable asset to any team. You are adept at conducting rapid studies, analyzing design issues, and proposing effective solutions. Your communication skills are exceptional, enabling you to present complex data clearly and effectively to both internal teams and external stakeholders. You are a thought leader who contributes to the technical community through journal articles, whitepapers, and patents. You are committed to continuous learning and staying abreast of the latest industry standards and technologies. Ultimately, you are passionate about making a significant impact on the future of SERDES technology.</p><h4>What You’ll Be Doing:</h4><ul><li>Reviewing SERDES standards and literature to develop novel transceiver architectures and sub-block specifications.</li><li>Independently and collaboratively working with design teams to conduct rapid studies of design issues, solutions, and trade-offs.</li><li>Working across analog/digital/layout/hardware functional domains to develop novel solutions to technical challenges.</li><li>Reviewing and presenting simulation data from internal project teams, and presenting results externally at industry panels or customer reviews.</li><li>Producing journal articles, technical whitepapers, and patents relating to SERDES IP design innovations.</li><li>Reviewing silicon data, proposing experiments, identifying root-causes, and proposing both short and long-term solutions.</li><li>Representing Synopsys externally at technical conferences, universities, and standards bodies.</li><li>Engaging with customers during pre and post-sales to help them achieve first-time success with our SERDES IP.</li></ul><h4>The Impact You Will Have:</h4><ul><li>Driving the innovation and development of high-performance SERDES IP.</li><li>Enhancing Synopsys' reputation as a leader in analog and mixed-signal design.</li><li>Contributing to the success of our customers by providing cutting-edge solutions.</li><li>Shaping the future of SERDES technology through your innovative designs and solutions.</li><li>Expanding Synopsys' portfolio of intellectual property through patents and technical publications.</li><li>Collaborating globally to push the boundaries of what is possible in SERDES design.</li></ul><h4>What You’ll Need:</h4><ul><li>MSc or PhD with 15+ years of practical analog IC design and SERDES system architecture experience.</li><li>In-depth familiarity with transistor level circuit design and sound CMOS design fundamentals.</li><li>Extensive design experience with sub-circuits relevant to SERDES, including ADC, DAC, receive equalizers, comparators, TX drivers, serializers, deserializers, VCO, DLL, and PLL.</li><li>Experience with different modulation schemes such as NRZ, PAM4, and others.</li><li>Solid understanding of Equalization and DSP techniques used in SERDES.</li><li>Knowledge of SERDES standards, fabrication, and hardware issues impacting customer use-cases.</li><li>Experience in analyzing link budgets for high-speed serial links.</li><li>Familiarity with modeling SERDES transmitters and receivers in Matlab or similar tools.</li><li>Experience with SPICE simulators and simulation methods.</li><li>Knowledge of scripting languages such as TCL, Perl, C, Python, or MATLAB.</li></ul><h4>Who You Are:</h4><ul><li>An innovative thinker with a passion for technology and continuous improvement.</li><li>A collaborative team player who thrives in a dynamic environment.</li><li>An excellent communicator with strong presentation and documentation skills.</li><li>A detail-oriented problem solver who can navigate complex challenges.</li><li>A leader who can influence and inspire others through your expertise and vision.</li><li>A lifelong learner committed to staying current with industry advancements.</li></ul><h4>The Team You’ll Be A Part Of:</h4><p>You will join an experienced analog and mixed-signal R&amp;D team, collaborating with leading SERDES IP experts. Our team is dedicated to developing innovative architectures, algorithms, and circuits to achieve best-in-class SERDES performance. We work in a world-class design environment, offering numerous opportunities for global collaboration and professional growth.</p><h4>Rewards and Benefits:</h4><p>We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.</p><p><span id="isPasted">At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.</span></p><h4>Experience Level</h4>Senior Level

Electronic Engineer

<p>PRINCIPAL SW SYSTEMS ENGINEER 9592- Routing Protocol Development</p><b>Roles &amp; Responsibilities:</b><br/>Experience: 15+ Years • Exposure to the entire Product Life Cycle • Micro services-based Architecture, working experience with Docker containers, Kubernetes (K8s, K3s) cluster, Helm charts • Strong coding and debugging experience using Golang or C • Linux OS, Data structures, IPC mechanisms. Understanding of multi-threading/routines. • Agile Development Model with CI/CD, Jenkins pipeline and working knowledge of Git environment. • Working knowledge of OpenConfig NETCONF/GNMI/GRPC • Proficiency in L2/L3 OSI layer Protocols - LACP ; LAGs; BGP ; BFD; EVPN; MPLS/VPLS; ARP; and L2 switching; L3 Routing • Good Written/Verbal Communication Skills<h4>Experience Level</h4>Senior Level

Extreme Networks India Private Limited

Assistant software Engineer

<p>Technologist, ASIC Development Engineering (Physical Design)</p><h4>Company Description</h4><p>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.</p><p>Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.</p><p>Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.</p><h4>Job Description</h4><p><strong>Position Overview:</strong></p><p>We are looking for a highly skilled and experienced individual for SoC PD lead position for driving SoC implementation efforts from RTL to GDSII. This role is pivotal within our talented team of engineers, ensuring that we meet our GDS release timelines, PPA requirements, and all sign-off criteria for our complex semiconductor designs. This role demands a profound technical understanding of the entire implementation cycle, from start to finish, as well as exceptional leadership skills. The successful candidate will work with various functional teams and must possess a strategic vision to drive continuous improvement in our methodologies and processes.</p><p> </p><p><strong>Key Responsibilities:</strong></p><ul><li>To be responsible for leading RTL-to-GDSII SoC implementation effort</li><li>To collaborate with cross-functional teams, including Design, Verification, Analog, DFT, SIPI etc.</li><li>To develop and guide the team members in their work, enhancing their technical capabilities and increasing productivity.</li><li>To ensure process compliance during project execution and enable / participate in technical discussions/reviews.</li><li>To prepare and submit status reports for minimizing exposure and risks on the project or closure of escalations.</li><li>Stay abreast of industry trends and emerging technologies in related fields, and incorporate best practices into the team’s workflow</li><li>Foster a culture of innovation, collaboration, and continuous improvement</li></ul><p>-</p><h4>Qualifications</h4><p>- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field</p><p>- A minimum of 13 to 15 years of experience in leading RTL to GDSII implementation effort across various SoCs</p><p> </p><ul><li>Proven ability in technically leading a small/medium-sized team for executing projects preferred.</li><li>Hands-on experience on the entire PD Flow from RTL to GDSII</li><li>Should have a good understanding of Floor planning, Power Planning, Placement &amp; Optimization, CTS, Routing, Design Convergence, and Sign-off with in-depth expertise in at least one of these domains.</li><li>Working knowledge about OCV, MM/MC optimization and multi-power designs (Level shifters, Isolation cells, etc)</li><li>Exposure to static timing analysis fixes including automated ECO generation.</li><li>Strong in areas on CTS, Power, Bump planning, Floorplan</li><li>Experience with tools (e.g., Synopsys FusionCompiler, PrimeTime, Cadence Innovus, Constraints Manager, Redhawk, Calibre etc.) and methodologies.</li><li>Library preparation in any environment (Synopsys, Cadence, etc)</li><li>Working knowledge on Physical verification tasks at lower nodes (database merging/DRC/LVS/ERC/PERC/Antenna/ESD/LUP analysis/fixing) at block level/chip level</li><li>The job would require complete ownership from RTL to GDS for complete SoC</li><li>Exposure to IP Hardening for blocks like SERDES, USB PHY, PCIe, DDR will be an added advantage.</li><li>Working knowledge of scripting languages like Perl and TCL will be considered a plus</li><li>Candidate needs to be self-driven and confident in reporting the status and sharing technical results with customers.</li><li>Must have the ability to present to senior management, work in a geographically dispersed team, and be aware of cross-cultural nuances.</li><li>Should be able to define project milestones, identify risks, and call out mitigation plans.</li></ul><p> </p><h4>Additional Information</h4><p>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.</p><p>Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at jobs.accommodations@sandisk.com to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying</p><h4>Experience Level</h4>Senior Level

<p>Principal Engineer, ASIC Development Engineering (IP Verification)</p><h4>Company Description</h4><p>Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.</p><p>Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.</p><p>Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.</p><h4>Job Description</h4><p>We are seeking a highly skilled and experienced Principal Engineer to join our ASIC Development Engineering team in Bengaluru, India.</p><p>In this role you will  design and implements IPs and subsystems.</p><p>Dealing the best of class IPs for all SanDisk products</p><ul><li>BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field</li><li>8+ years of experience in ASIC development, with a proven track record of leading complex project</li><li>At  hands on in IP / blocks / subsystem complex design in verilog / sysverilog</li><li>Strong digital design development and execution skills , solving bugs</li><li>Experience in grooming team of 1-4 engineers, interacting with many team</li><li>Deep expirience in debug , solving problem, see the architecture view, proposing solutions.</li><li>Hands-on experience with industry-standard EDA tools and design flows </li><li>Deep knowledge on PCIe,  axi , DMA, AHB interfaces </li><li>Experience in Verification UVM ,  DDR , flash is a plus</li><li>BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field</li><li>Expertise in high-performance and low-power design techniques</li><li>Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly</li></ul><p> </p><h4>Qualifications</h4><ul><li>BE or Master's in Electronics  Engineering,  Electrical Engineering, Computer Engineering, or related field</li><li>10+ years of experience in ASIC development, with a proven track record of leading complex projects</li><li>Advanced knowledge of ASIC design and development, including digital design, verification methodologies, and proficiency in hardware description languages (e.g., Verilog, VHDL)</li><li>Expertise in high-performance and low-power design techniques, with hands-on experience using industry-standard EDA tools</li><li>Strong problem-solving, debugging, and analytical skills to resolve complex technical issues</li><li>Excellent leadership, mentoring, and communication skills, with the ability to guide engineering teams and articulate complex technical concepts</li><li>Understanding of semiconductor industry trends and willingness to work in Bengaluru, India, with occasional travel</li></ul><h4>Additional Information</h4><p>Sandisk thrives on the power and potential of diversity. As a global company, we believe the most effective way to embrace the diversity of our customers and communities is to mirror it from within. We believe the fusion of various perspectives results in the best outcomes for our employees, our company, our customers, and the world around us. We are committed to an inclusive environment where every individual can thrive through a sense of belonging, respect and contribution.</p><p>Sandisk is committed to offering opportunities to applicants with disabilities and ensuring all candidates can successfully navigate our careers website and our hiring process. Please contact us at <a href="mailto:jobs.accommodations@sandisk.com">jobs.accommodations@sandisk.com</a> to advise us of your accommodation request. In your email, please include a description of the specific accommodation you are requesting as well as the job title and requisition number of the position for which you are applying.</p><h4>Experience Level</h4>Senior Level

Chief Engineer

<p>Senior Logic Design Engineer</p><p><span>Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.</span></p><p><span> </span></p><p><span>As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the <strong>Cloud Compute Development Organization (CCDO) </strong>is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. </span></p><p><span> </span><span>We are looking for an <strong>SOC RTL to PD Engineer</strong> to join the team.</span></p><p><span> </span></p><p><span>#azurehwjobs</span><span>   </span></p><h4>Responsibilities</h4><ul><li><span>Ensure high quality deliverables from RTL to Physical Design</span></li><li><span>Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results</span></li><li><span>Create, analyze, and maintain timing constraints/SDCs</span></li><li><span>Analyze and drive UPF solutions for low power checks</span></li><li><span>Drive RTL to Synthesis FEV clean</span></li><li><span>Collaborate with RTL and Physical Design team to address design feedback and drive quality</span></li></ul><h4>Qualifications</h4><ul><li><span>Required Qualifications:</span><ul><li><span>MS with 5+ years of experience or BS with 7+ years of experience. </span></li><li><span>At least 5+ years of experience applying digital design principles in SOC and/or IP development. </span></li><li><span>Strong Static Timing Analysis background; understanding timing signoff fundamentals. </span></li><li><span>Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, and Innovus. </span></li><li><span>Experience with timing constraints management and debug tools supporting constraints quality checks, constraints verification, constraints promotion &amp; demotion. </span></li><li><span>Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints. </span></li><li><span>Understanding in design closure challenges in power and clock domain crossings. </span></li><li><span>Understanding reset and FIFO related design requirements.</span></li></ul></li><li><span>Preferred Qualifications</span><ul><li><span>Experience with FEV and industry standard tools such as Formality and/or Conformal</span></li><li><span>Applied understanding of low power design principles. </span></li><li><span>Highly Proficient in Verilog/System Verilog coding constructs. </span></li><li><span>Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) </span></li><li><span>Strong understanding in clock crossing techniques </span></li><li><span>Strong understanding in IJPF (Low power intent). </span></li><li><span>Ability to write scripts using Perl, TCI, Python etc. </span></li><li><span>Familiarity with Industry standard interface protocols is a plus. </span></li><li><span>Good verbal and written communication skills. </span></li></ul></li></ul><p><span>Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application or the recruiting process, please send a request via the <a href="https://careers.microsoft.com/us/en/accommodationrequest" rel="noopener" target="_blank">Accommodation request form</a>.</span></p><p> </p><p><span>The ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </span></p><p> </p><p><span>Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.</span></p><h4>Experience Level</h4>Senior Level

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