Silicon Micro-architecture Design Lead, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in ASIC/SoC development with Verilog/SystemVerilog.
• Experience in micro-architecture and design of IPs and Subsystems.
• Experience in ASIC/SoC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Preferred qualifications:

• Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• Experience with coding languages (e.g., Python or Perl).
• Experience in System on a Chip (SoC) designs and integration flows.
• Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.
• Knowledge of high-performance and low-power design techniques.

About the job

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Lead a team of Engineers in the design organization to deliver complex IPs or Subsystems. Communicate and work with multi-disciplined and multi-site teams.
• Define micro-architecture (uArch) specifications and block-level design documents, including interface protocols, block diagrams, transaction flows, and pipeline details.
• Perform RTL development, subsystem integration, and System on a Chip (SoC) integration, as well as Lint, CDC, FV, and UPF checks.
• Participate in simulation debug, synthesis, timing and power closure, and silicon bring-up.
• Participate in test plan and coverage analysis of the block and SOC-level verification.