Sr. Principal Design Engineer

Sr. Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

1. Role Overview & Objective

• We are looking for a motivated SRAM Circuit Design Engineer to join our semiconductor engineering team developing circuits and SRAM/Register File for low power, low voltage and high performance.
• This role is ideal for candidates who are passionate about memory design, characterization methodologies, and physical verification, and who are eager to build a strong foundation in VLSI memory development.

2. Key Responsibilities

• Circuit Design & Optimization: Build full-custom or compiler-based SRAM macros, sense amplifiers, and self-timed circuits.
• Simulation & Characterization: Run SPICE simulations to analyze timing, power, and Static Noise Margin (SNM) across process corners.
• Layout Supervision: Direct physical design and layout teams to handle process variability and FinFET manufacturing rules.
• Silicon Validation & Debug: Support post-silicon testing and troubleshooting hardware failures

3. Required Qualifications & Experience

• Education: B.Tech/M.Tech in Electrical Engineering, VLSI, or Microelectronics.
• Experience: Typically ranges from 6 to 18 years depending on whether the role is entry/mid-level or a senior lead/architect position.

• Core Knowledge: Deep understanding of CMOS device physics, transistor sizing, and memory cell stability.
• Tools: Proficiency in EDA software like Cadence Virtuoso or SPICE simulators.
• Scripting: Ability to use Python or Perl for workflow automation and data analysis

4. Behavioral & Soft Skills

• Strong analytical and problem-solving skills.
• High attention to detail.
• Ability to collaborate cross-functionally with circuit designers, architecture teams, and CAD engineers.

We’re doing work that matters. Help us solve what others can’t.

Experience Level

Senior Level