DFT Engineer III, Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  
• 4 years of experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow, DFT EDA Tool (Tessent).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science or a related field.
• Knowledge of high performance design DFT techniques.
• Understanding of the end to end flows, Design, Verification, DFT and PD.
• Proficiency in Synthesis, Lint, LEC and DFT timing and STA.
• Proficiency in a scripting language such as Perl, Python.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As an ASIC DFT Engineer, you will be a member of the Silicon SOC DFT team responsible for Optimizing test time and achieving coverage targets for our next generation pixel phones. In this role, you will focus on SOC DFT execution activities from RTL to silicon bringup.

Responsibilities

• Work on SOC DFT Architecture, implement and validate from SOC level.
• Work closely with RTL, Physical Design (PD) team at SOC level and also with the subsystem DFT teams.
• Write basic to complex scripts to automate the DFT flow and develop tests that can be used for production in the ATE flow.