Staff VLSI Design Engineer (CAD)

Staff VLSI Design Engineer (CAD)

Company Description

Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today’s needs and tomorrow’s next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we’re living in and that we have the power to shape.

 

Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality.

 

Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward.

Job Description

• Responsible for the further development of concepts and methods for the EDA design environments with focus on analog / mixed signal CAD flows.
• Expert level proficiency in one or more of the programming/scripting languages – SKILL, Python, Unix, Perl and TCL.
• Expertise in Virtuoso suite of tools and Analog Design environment (finesim/PrimeSim)
• Solid understanding of Calibre Physical Verification rule deck (SVRF) and ICV LVS decks with hands on experience in integrating various PV flows in CAD environment.
• Solid experience in Layout Automation and Utilities development in Cadence SKILL/SKILL++.
• Development and validation of PV tools and flows like parasitic extraction, EMIR drop and substrate noise analysis.
• Responsibilities will include testing, validation, customer support and new tool/methods evaluations, development of methods and procedures for quality improvement, automation of deck/tech Files generation and validation.
• Experience with Cadence custom IC Virtuoso platform to create layout test structures, to validate verification rules and to troubleshoot errors.
• Experience with physical verification tools for parasitic extraction (starRC) is a plus.
• Working knowledge of revision control software (Git, Perforce, Synchronicity, etc)
• Ensuring the operation and support within the CAD for layout and circuit designers worldwide.
• Develop and deploy agentic AI flows to automate flow execution, detect bottlenecks, triage violations, and drive closure decisions without manual intervention

Qualifications

• Education: University degree (Master) in Electronics/Electrical engineering or a comparable subject
• Experience and Knowledge: Minimum 7+ years of development experience of Mixed Signal CAD design Flows from Front to Back, expert knowledge and experience of state-of-the-art design tools (EDA-vendors e.g. Cadence, Synopsys, Mentor) and Software-development-methodologies and tools (Linux, script- and programming-languages as well as Cadence Skill), thorough understanding of Custom Analog development flow, design tools and Software / Hardware environment
• Qualifications: Ability to identify and analyze tasks efficiently within the scope of your work and to develop pragmatic application-specific solutions; pronounced ability to communicate, relevant experience in the methodology of problem solving as well as in the cooperation and leadership of international and cross-functional teams
• Technical Skills: Cadence SKILL, StarRC, Totem. Calibre SVRF/TVF, Python, Shell Scripting.
• Languages: fluent in English

Additional Information

All your information will be kept confidential according to EEO guidelines.

Experience Level

Senior Level