Silicon Circuit Digital Design Engineer, Cloud Silicon

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience with mixed-signal analog integrated circuit design, or equivalent practical experience.
• Experience with analog circuits, simulation, clocks, and analog design.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Simulate and optimize clock tree networks with respect to key clock quality metrics.
• Evaluate clock IPs such as PLLs, FLLs, other adaptive systems involving ADCs, clock drivers, receivers and differential buffers.
• Perform detailed jitter compliance simulations for Serdes, PCIe reference clocks and other high speed clocks.
• Guide sub-system clocking on best practices in terms of clock quality.
• Provide inputs to timing and sign-off teams on clock inputs such as jitter, duty-cycle, and aging margins.