Silicon Networking Lead, Google Cloud

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 15 years of experience in ASIC design and development.
• Experience leading multi-disciplinary silicon engineering teams through the full development life-cycle from architecture definition to tape-out.
• Experience in high-performance or low-power design techniques, ASIC standard interfaces, and memory system architectures.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with ASIC standard interfaces and memory system architecture.
• Knowledge of high-performance and low power design techniques.
• Knowledge of FPGA, emulation platforms, and SOC architecture.
• Knowledge of one of the following areas: arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies.

About the job

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Own the Silicon Networking organization in Bengaluru, including definition, implementation and deployment of Networking IPs. Define IP development methodologies and drive deep technical involvement across the IP's development cycle, including seamless integration to SoC.
• Lead project planning from architecture and micro-architecture decisions to scoping effort, collaborating across teams to represent project status. Lead and manage a multi-disciplinary team of chip engineers, plan tasks, allocate people, and hold technical design/code reviews.
• Guide and participate across the entire ASIC lifecycle, spanning architecture definition, RTL development, synthesis, timing/power, FPGA/silicon bring-up, and verification strategy.
• Drive the full development life-cycle of chips from initial definition to a high-quality tape-out. Ensure developed IPs contribute effectively across multiple key projects.
• Collaborate closely with cross-functional teams and other sites around the globe.