DFT Design Engineer - Foundry Team

As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers get to work across diverse domains, projects, products, clients, people and countries, and conduct research in new and emerging technology areas. Innovation and creativity are highly valued at this innovation hub, as we strive towards providing high reliability; high performance and value added services that enable Samsung Electronics deliver world-class products. 

Roles and Responsibilities

5+ years of experience in full chip DFT architecture, implementation, timing closure and post silicon validation. Expertise required in the following areas:

• Scan architecture planning, pin mixing and scan compression planning, optimization for pattern volume for SA and TD pattern sets, scan synthesis, power optimization techniques in test modes
• MBIST architecture planning, repair architectures, insertion, verification
• Analog and mixed signal IP testing architecture and verification including IPs such as PLLs, PHYs
• Timing closure of scan, MBIST and other test modes, writing SDCs, understanding of timing exceptions wherever required, debugging timing issues with PD team
• Timing GLS, debug of fails in simulations
• Post silicon validation, interpretation of tester results, debugging IR drop issues, diagnostics of silicon failures
• Understanding of JTAG operation and debug required. Understanding of iJTAG protocol desirable
• Understanding of functional test cases, IO testing, testing of ARM processor cores
• Ability to lead a team across all aspects of DFT, interact with RTL, physical design teams for DFT implementation, anticipate risks, plan project timelines and milestones

Experience – 5+ Years

Qualifications

• B.Tech/B.E/M.Tech/M.E