Lead Design Engineer

Analog Mixed-Signal Lead Design Engineer (T3) – SerDes 

Position Summary 

We are seeking an Analog Mixed-Signal Lead Design Engineer (T3) to develop high-speed, low-power SerDes transceivers for data-center, networking, AI, and high-performance computing applications. The engineer will translate system requirements into silicon-ready circuit architectures and collaborate with the architecture, digital, layout, verification, signal integrity, and post-silicon teams. 

Key Responsibilities 

• Design and verify high-speed SerDes blocks, including TX drivers, serializers, RX front ends, CTLEs, samplers, comparators, ADCs, DACs, PLLs, DLLs, clock dividers and distribution networks, regulators, bias circuits, and calibration loops. 

• Translate link-level requirements into circuit specifications and optimize performance across PVT, mismatch, aging, and extracted parasitics. 

• Develop behavioral models and support mixed-signal and top-level verification. 

• Collaborate with layout and signal-integrity teams on physical implementation, channel/package effects, and post-layout signoff. 

• Support tapeout, silicon bring-up, characterization, debug, and production release. 

• Document results and participate in technical design reviews. 

Required Qualifications 

• B.S. in Electrical Engineering or a related field with 3+ years of relevant experience, or an M.S. with 1+ years. 

• Strong analog CMOS, noise, jitter, feedback, signal-integrity, and data-converter fundamentals. 

• Hands-on transistor-level design experience with high-speed SerDes circuits. 

• Excellent command of Cadence Virtuoso, Spectre, Spectre RF, ADE, parasitic extraction, and mixed-signal verification flows. 

• Strong analytical, communication, collaboration, and engineering judgment. 

Preferred Qualifications 

• Experience with PAM4/NRZ SerDes, advanced CMOS or FinFET technologies, and standards such as Ethernet, PCIe, or CXL. 

• MATLAB or C for architecture development; SystemVerilog or Verilog-A for functional modeling; and Perl or Python for automation. 

• Experience using AI-assisted engineering tools responsibly for design exploration, verification, debugging, documentation, and workflow automation. 

• Custom analog layout experience is a plus. 

• Lab characterization experience is a plus, along with experience taking mixed-signal IP from architecture through tapeout and silicon validation. 

Success in This Role 

The ideal candidate combines strong circuit intuition, disciplined verification, ownership, and clear communication to deliver reliable, power-efficient SerDes solutions.