CPU Design Verification Engineer, Core IP

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in verification of IPs, Subsystems and SoCs.
• 8 years of experience in creating design verification strategies and plans, constraint random verification with SystemVerilog (SV) and Universal Verification Methodology (UVM).
• 8 years of experience in verifying multi-stage, high-performance CPU core and related peripherals, RISC-V architecture and ISA extensions.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with low power, debug, performance verification and use cases verification.
• Experience with Security IP and subsystems.
• Familiarity with scripting languages (Python, Perl, or Tcl).
• Interest in AI-assisted IP Verification Methodologies.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Design Verification Engineer, you will be a key member of the team responsible for Verifying our next-generation RISC-V processor cores. In this role, you will focus on verifying architecture features, including standard or custom RISC-V Instruction Set Architecture (ISA) extensions. You will leverage your deep expertise in verifying CPU Architecture and ensure high quality Design Verification (DV) sign-off. This includes building verification infrastructure, testbenches, planning, metrics development and convergence of metrics to deliver high quality CPU cores and related peripherals.

Responsibilities

• Work with designers, architects and other stakeholders to come up with detailed test plans, dependencies and deliverables.
• Plan the verification of RISC V CPU cores and related peripherals by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
• Work closely with Architecture, software, design stakeholders to make technical decisions. Create and enhance constrained-random verification environments using System Verilog and UVM. Represent DV status throughout the development process.
• Take technical decisions independently and ensure momentum for the project. Set the goal and own IP verification methodology. Identify methodology improvements.
• Partner with Pre-Silicon (Si) and Post-Si Validation teams for successful bring up of the IP.